Resistive Networks and Circuit Laws

• Series and parallel combinationSeries resistances add. Parallel conductances add. The parallel result is always smaller than the smallest member — a useful sanity check that catches arithmetic slips instantly.R_series = R1 + R2 + ... ; 1/R_parallel = 1/R1 + 1/R2 + ... ; for two: R1*R2/(R1+R2).
• Kirchhoff's Current Law (KCL)Charge does not pile up at a node, so the currents entering a node equal the currents leaving it. This is the law you use to reason about supply current budgets and about where return current actually goes.Sum of currents into any node = 0.
• Kirchhoff's Voltage Law (KVL)Walk any closed loop and the voltage rises must equal the voltage drops. This is how you find the voltage at a node that isn't directly connected to a source, and how you spot an impossible schematic.Sum of voltages around any closed loop = 0.
• The voltage divider and its loading trapTwo resistors from a supply produce a fraction of that supply — but only while nothing draws current from the midpoint. As soon as you load it, the effective lower-leg resistance drops and the output sags. The rule of thumb is to make the divider current at least 10x the load current.Vout = Vin x R2 / (R1 + R2), unloaded.
• The current dividerCurrent entering parallel branches splits in inverse proportion to their resistances. The low-resistance branch takes the larger share. This is the mental model for why current takes the path of least impedance, not exclusively the path of least resistance.I1 = I_total x R2 / (R1 + R2) for two parallel branches.
• Thevenin equivalentAny network of sources and resistances, seen from two terminals, behaves identically to one voltage source in series with one resistance. Collapsing a divider to its Thevenin equivalent is the fastest way to answer 'what happens when I connect this to something'.Vth = open-circuit voltage. Rth = resistance seen with sources zeroed (V sources shorted, I sources opened).
• Tolerance stack-upReal resistors are 1% or 5%. A divider built from two 5% parts has a worst-case output error of roughly 10% of the ratio, not 5%. When a divider sets a regulator's feedback or an ADC reference, tolerance is a design input, not an afterthought.

ProblemYou need 3.3 V from a 5 V rail to feed a sensor that draws 1 mA. A colleague proposes a divider of R1 = 17 k and R2 = 33 k. Will it work?

1. 1
   Unloaded output: Vout = 5 x 33k/(17k + 33k) = 5 x 0.66 = 3.30 V. Looks correct.
2. 2
   Divider bleed current: I = 5 V / 50 k = 100 uA.
3. 3
   The load draws 1 mA — that is 10x the divider current, the exact inverse of the rule of thumb.
4. 4
   Find the Thevenin equivalent seen by the sensor: Vth = 3.30 V, Rth = 17k || 33k = 17*33/50 = 11.2 k.
5. 5
   Loaded output: the 1 mA load drops 1 mA x 11.2 k = 11.2 V across Rth. That is more than the source can supply, so the output collapses toward ground.
6. 6
   Solve properly: the load looks like 3.3 V / 1 mA = 3.3 k in parallel with R2. R2_eff = 33k || 3.3k = 3.0 k. Vout = 5 x 3.0/(17 + 3.0) = 0.75 V.
7. 7
   The sensor sees 0.75 V, not 3.3 V. The circuit is broken.

AnswerNo. Rth = 11.2 k is far too high for a 1 mA load; the output sags to about 0.75 V. A divider is the wrong tool here — use an LDO regulator. If a divider must be used for a high-impedance node, size it so divider current >= 10x load current (here, R1+R2 <= 500 ohm), and accept the 10 mA of standing waste.

Tool: ngspice (open source SPICE simulator)

• Install ngspice (macOS: brew install ngspice; Debian/Ubuntu: sudo apt install ngspice; Windows: download from the project site).
• Create divider.cir with this content:

  Loaded voltage divider
  V1 in 0 DC 5
  R1 in out 17k
  R2 out 0 33k
  Rload out 0 3.3k
  .op
  .end

• Run: ngspice -b divider.cir
• Read the operating point printout. v(out) should be about 0.75 V, matching the hand calculation.
• Comment out the Rload line (prefix with *) and re-run. v(out) should now be 3.30 V.
• Change R1 to 170 and R2 to 330 (100x lower), restore Rload, re-run. v(out) should now be close to 3.3 V — the stiff divider survives the load.
• Add a .dc sweep to see the whole curve: replace .op with '.dc V1 0 5 0.1' and add '.print dc v(out)'. Confirm the transfer is linear.

• DC Electrical Circuit Analysis (Fiore) - Chapters 3 to 6open licencereading~180 minSeries/parallel, source conversions, nodal and mesh analysis, then Thevenin/Norton. Work the examples with a pen, not by reading.
• MIT OCW 6.002 Circuits and Electronics - Lectures 1 to 3open licencecourse~150 minCC BY-NC-SA. The lumped matter discipline framing in lecture 1 is worth the time on its own — it tells you when circuit theory stops being valid.
• Electronics Tutorials - DC Circuits sectionfreereading~60 minGood worked-example density for dividers, KCL/KVL and Thevenin. Use for extra practice problems.
• ngspice user manualopen licencedoc~45 minRead only chapter 2 (circuit description) and the .op / .dc / .tran sections of chapter 15. Keep it open as a reference for the whole track.

You are handed a 12 V supply and asked to produce three reference voltages for a test jig: 6 V feeding a 10 k load, 3.3 V feeding a 1 M load, and 1.0 V feeding a 100 ohm load. Design each one, and where a resistive divider is the wrong answer, say so and prove it.

Deliverables

• For each of the three outputs: a hand analysis producing the divider values, the Thevenin equivalent (Vth and Rth), the loaded output voltage, the divider standing current, and the total power burned.
• An ngspice netlist for all three dividers with their loads, plus the .op output pasted in, showing simulated node voltages.
• A written verdict per output: 'divider is acceptable because...' or 'divider is unacceptable because... and the correct solution is...'. At least one of the three must be rejected with numbers.
• A worst-case tolerance analysis of the 3.3 V output assuming 5% resistors: what are the minimum and maximum possible output voltages?

Acceptance criteria — how you know it is good enough

• Thevenin resistance is computed correctly for every output.
• The loaded output voltage is computed, not just the unloaded one.
• The 100 ohm load case is correctly identified as unsuitable for a divider, with the power waste quantified.
• Simulated results agree with hand analysis to within 2%.
• The tolerance analysis uses worst-case opposite-corner values, not a single nominal figure.

If you want to push further

• Redesign the 1.0 V output using a resistor and a single Zener or a TL431 shunt reference; compare regulation under a 50% load change against the divider.
• Write a small script (Python, or a spreadsheet) that takes Vin, Vout and load current and returns the E24 divider pair with the lowest error.

• I can reduce any series-parallel resistor network to a single equivalent by hand.
• I can apply KCL and KVL to solve for an unknown node voltage in a two-loop circuit.
• I can find the Thevenin equivalent of a divider and use it to predict the loaded output.
• I can state the 10x rule for divider stiffness and explain the trade-off against standing current.
• I can write, run and read a simple ngspice netlist without a schematic editor.
• I can do a worst-case tolerance analysis on a two-resistor divider.