Op-Amps and Signal Conditioning

• The two golden rulesWith negative feedback and within its limits, an ideal op-amp drives its output so that the two inputs are at the same voltage, and it draws no input current. Almost every standard configuration falls out of applying these two rules plus KCL at the inverting node.V+ = V-, and I_in = 0. Then apply KCL at the summing junction.
• The standard blocksBuffer (gain 1, high input impedance), non-inverting amplifier (gain 1 + Rf/Rg, always >= 1), inverting amplifier (gain -Rf/Rin, input impedance = Rin), difference amplifier, and summing amplifier. Learn to derive each rather than memorising the formulas.Non-inverting: G = 1 + Rf/Rg. Inverting: G = -Rf/Rin. Buffer: G = 1.
• Real op-amps have limits that biteInput offset voltage adds a DC error multiplied by your gain. Input bias current develops an error across your source resistance. Slew rate limits how fast the output can move. Gain-bandwidth product means your gain of 100 has only GBW/100 of bandwidth. The output cannot reach the rails unless the part says rail-to-rail, and even then not under load.Available bandwidth = GBW / closed-loop gain. Output DC error ~ Vos x closed-loop gain.
• Single supply and the virtual mid-railMost modern designs run from a single rail. To handle bipolar signals you create a reference at mid-rail, usually with a divider buffered by a spare op-amp, and treat that as your new zero. Using an unbuffered divider as a reference is a classic mistake — see the loading trap from the divider skill.
• Anti-alias filtering before an ADCAny signal component above half the sample rate folds back into your data as a false low-frequency signal you can never remove afterwards. An RC or active filter before the ADC is mandatory, and its corner must be set from the sample rate, not from the signal.Nyquist: sample at > 2x the highest signal frequency. Place the anti-alias corner well below Fs/2.
• Stability and capacitive loadsAn op-amp driving a capacitive load (like an ADC input or a long cable) can ring or oscillate because the load adds a pole inside the feedback loop. The standard fixes are a small series isolation resistor, or a feedback capacitor to roll off the loop.

ProblemA sensor produces -10 mV to +40 mV. You must map this to the 0.1 V to 3.2 V input window of a 3.3 V, 12-bit ADC using a single 3.3 V supply.

1. 1
   Input span: 40 - (-10) = 50 mV. Output span: 3.2 - 0.1 = 3.1 V. Required gain = 3.1 / 0.05 = 62.
2. 2
   Required output offset: when Vin = -10 mV, Vout must be 0.1 V. With gain 62, the signal contributes 62 x -0.010 = -0.62 V, so we need +0.72 V of offset added.
3. 3
   Use a difference amplifier: Vout = G x (Vin - Vref_in) + Vref_out, or more simply a non-inverting stage referenced to a small offset voltage.
4. 4
   Choose the offset source: 0.72 V / 62 = 11.6 mV referred to the input. Generate it with a divider from 3.3 V and buffer it. 3.3 V x R2/(R1+R2) = 11.6 mV needs a ratio of 285:1 — awkward and noise-sensitive.
5. 5
   Better: split into two stages. Stage 1 non-inverting gain of 10 referred to ground. Stage 2 difference amplifier with gain 6.2 and a 0.12 V reference. Total gain 62.
6. 6
   Check the op-amp's DC error: with 62x total gain, an op-amp with Vos = 3 mV contributes 3 mV x 62 = 186 mV of output error — 6% of full scale. Unacceptable. Choose a precision part with Vos < 100 uV (a chopper/zero-drift amplifier, Vos ~ 5 uV, is the right class here).
7. 7
   Check bandwidth: if the signal is slow (thermal, < 10 Hz), a GBW of 1 MHz gives 1 MHz/62 = 16 kHz of closed-loop bandwidth. Vastly sufficient.
8. 8
   Anti-alias: sampling at 100 Hz, set the RC corner at 10 Hz. R = 16 k, C = 1 uF gives f_c = 9.9 Hz.
9. 9
   Output rail check: the op-amp must swing to 0.1 V and 3.2 V on a 3.3 V supply, so a rail-to-rail output part is required. Verify the output swing spec at your load current, not the headline claim.
10. 10
    Add a 100 ohm series resistor and 1 nF to ground at the ADC input to isolate the op-amp from the ADC's sampling capacitor.

AnswerTwo-stage: non-inverting gain 10, then a difference stage of gain 6.2 with a buffered 0.12 V reference. Zero-drift rail-to-rail op-amp (Vos < 50 uV). 10 Hz anti-alias RC. 100 ohm + 1 nF ADC isolation network.

Tool: ngspice with an op-amp macromodel

• Download a free vendor SPICE macromodel for a rail-to-rail op-amp (TI, Analog Devices and Microchip all publish these). Save as opamp.lib.
• Build stage 1 as a non-inverting amplifier with Rg = 1k and Rf = 9k for a gain of 10.
• Add a DC sweep of the input from -10 mV to +40 mV: .dc Vin -0.010 0.040 0.0005
• Run and: plot v(out) — confirm the output spans the range you predicted and is linear across it.
• Add the second stage and re-sweep the whole chain. Check both endpoints land on 0.1 V and 3.2 V.
• Deliberately inject an offset error: add a small DC source in series with the non-inverting input, set to 3 mV, and re-run. Measure how much the endpoints shift. This makes the Vos argument concrete.
• Run an AC analysis: .ac dec 20 0.1 1meg and plot db(v(out)). Find the -3 dB point and check it against GBW / gain.
• Add the anti-alias RC and confirm the corner moves to 10 Hz.
• Add a 100 pF capacitive load directly on the output with no isolation resistor and run a transient step. Look for ringing. Then add the 100 ohm isolation resistor and observe it damp out.

• Operational Amplifiers and Linear Integrated Circuits (Fiore)open licencereading~240 minOpen textbook, CC BY-NC-SA. The single best free op-amp text. Chapters 1-5 cover ideal behaviour, real limits, and the standard configurations.
• Operational Amplifiers: Theory and Practice (Roberge)open licencereading~120 minThe MIT op-amp text, open-licensed on LibreTexts. Deeper than Fiore on feedback and stability — read the chapters on the effects of feedback and on compensation once the basics are solid.
• MIT OCW 6.002 - Op-amp lecturesopen licencecourse~120 minLectures on the op-amp abstraction and negative feedback. CC BY-NC-SA.
• TI TINA-TI or the vendor's free SPICE macromodelsfreetoolIf ngspice macromodel wrangling gets in the way, this free (proprietary) simulator loads vendor models with zero friction. Prefer ngspice where you can; use this when a model refuses to converge.

Take a real sensor with a published transfer function — a load cell, an NTC thermistor, a current shunt, or a photodiode — and design the complete analogue front end that maps its full output range onto the input window of a 3.3 V, 12-bit ADC sampling at a rate you specify.

Deliverables

• The sensor's datasheet link and its transfer function, with the minimum and maximum expected output stated in volts (or amps, converted).
• A gain and offset calculation mapping that range onto your chosen ADC window, with the topology chosen and justified.
• An op-amp selection with a real part number, and a table showing that its Vos, input bias current, GBW, output swing and supply range all satisfy your design, each with the number and the requirement side by side.
• An error budget in LSBs: offset error, gain error from resistor tolerance, noise, and quantisation. State your effective resolution in bits and whether the 12-bit ADC is being wasted.
• An anti-alias filter design with the corner derived from your sample rate, plus the ADC input isolation network.
• An ngspice DC sweep proving the endpoint mapping, and an AC analysis proving the filter corner.
• A schematic drawn in KiCad (schematic only, no layout) with all values annotated.

Acceptance criteria — how you know it is good enough

• The DC transfer maps the sensor's full range into the ADC window with at least 5% headroom at both ends.
• The op-amp's specified output swing at the actual load is checked, not assumed.
• The error budget is expressed in LSBs and the dominant error source is named.
• The anti-alias corner is derived from the sample rate, not chosen arbitrarily.
• The simulation endpoints match the hand calculation within 2%.
• The design works from a single 3.3 V supply with no negative rail.

If you want to push further

• Add a second-order Sallen-Key anti-alias filter and compare its stopband attenuation at Fs/2 to the single RC.
• Add ratiometric referencing (drive the sensor bridge from the ADC reference) and explain which error terms this cancels.

• I can derive the gain of any standard op-amp configuration from the two golden rules.
• I can map an arbitrary sensor range onto an ADC window with the right gain and offset.
• I can read Vos, Ib, GBW, slew rate and output swing off a datasheet and say which one limits my design.
• I can build a single-supply signal chain without a negative rail.
• I can set an anti-alias corner from a sample rate and explain what aliasing does.
• I can produce an error budget in LSBs and name the dominant term.