Logic Levels and Interfacing

• The four numbers that decide compatibilityVOH and VOL are what a driver guarantees to produce. VIH and VIL are what a receiver guarantees to accept. Compatibility means driver VOH(min) > receiver VIH(min) and driver VOL(max) < receiver VIL(max), with margin. Everything else in this skill is a consequence.Check VOH(min) >= VIH(min) and VOL(max) <= VIL(max). Both directions, both conditions.
• Noise marginThe gap between what the driver guarantees and what the receiver requires is your noise margin. A design with 100 mV of margin will work on the bench and fail in the field. CMOS families typically give volts of margin at the same supply; mixed-voltage interfaces often give almost none.NM_high = VOH(min) - VIH(min). NM_low = VIL(max) - VOL(max). Aim for hundreds of millivolts.
• Family differences: TTL, LVTTL and CMOS thresholdsCMOS thresholds scale with supply (roughly 0.3 Vcc and 0.7 Vcc); TTL and LVTTL thresholds are fixed at 0.8 V and 2.0 V. This is why a 3.3 V CMOS output drives a 5 V TTL input fine (3.3 > 2.0) but a 3.3 V output into a 5 V CMOS input fails (3.3 < 0.7 x 5 = 3.5). The same two chips, opposite answers, depending on family.
• 5 V tolerance and input protection diodesMost CMOS inputs have clamp diodes to the supply rail. Driving an input above Vcc + 0.3 V injects current through that diode; enough current and you either damage the part or, worse, power the whole chip through its input pin (a latch-up hazard). '5 V tolerant' means the manufacturer explicitly removed or rated this path — check the datasheet, do not assume.
• Push-pull versus open-drainA push-pull output actively drives both high and low; two of them fighting on one net is a short circuit. An open-drain output only pulls low and relies on an external pull-up, which allows multiple devices on one wire (wired-AND) and inherently shifts levels to whatever the pull-up rail is. I2C, interrupt lines and reset lines are open-drain for this reason.
• Sizing a pull-upToo large and the rise time is slow (RC against the bus capacitance), causing timing failures. Too small and the driver cannot pull low within its VOL spec at its rated sink current. Both limits are computable from datasheet numbers; the answer is a window, not a value.R_min = (Vdd - VOL_max) / I_OL_max. R_max = t_rise / (0.847 x C_bus) for a 30-70% rise.
• Level shifting techniquesResistive divider (down only, slow, cheap). Series resistor into a clamp (crude). Single-MOSFET bidirectional shifter (the classic I2C circuit, open-drain only, limited speed). Dedicated level-shifter IC (fast, directional or auto-sensing, the right answer for push-pull signals). Choose from the signal's direction, speed and drive type.
• Unused and floating inputsA floating CMOS input sits near the threshold, oscillates, and draws large shoot-through current in the input stage. Every unused input must be tied high or low — through a resistor if it might ever be driven, directly if it never will. This is a real reliability and power issue, not a formality.

ProblemA 3.3 V microcontroller talks I2C at 400 kHz to two sensors, one 3.3 V and one 1.8 V. Total bus capacitance is estimated at 150 pF on the 3.3 V side. Design the pull-ups and the level shift.

1. 1
   Level shift first: I2C is open-drain, so the standard single-MOSFET bidirectional shifter works. One small-signal N-channel MOSFET per line, source to the 1.8 V side, drain to the 3.3 V side, gate to 1.8 V.
2. 2
   For this to work the MOSFET's Vgs(th) must be well below 1.8 V. Check a real part: a BSS138 has Vgs(th) between 0.8 and 1.5 V. The 1.5 V maximum leaves only 0.3 V of overdrive — marginal. A part with Vgs(th) max of 1.0 V is a better choice.
3. 3
   Now the pull-ups. The circuit needs a pull-up on both sides: one to 3.3 V, one to 1.8 V.
4. 4
   R_min from the sink capability. I2C fast mode requires devices to sink 3 mA while holding VOL below 0.4 V. R_min = (3.3 - 0.4) / 0.003 = 967 ohm on the 3.3 V side. On the 1.8 V side: (1.8 - 0.4) / 0.003 = 467 ohm.
5. 5
   R_max from the rise time. I2C fast mode allows a maximum rise time of 300 ns. The bus rises exponentially from VIL to VIH, conventionally 30% to 70% of the rail, which takes 0.847 x R x C. So R_max = 300e-9 / (0.847 x 150e-12) = 2361 ohm on the 3.3 V side.
6. 6
   The window on the 3.3 V side is therefore 967 to 2361 ohm. Choose 1.5 k (E24) — comfortably inside, closer to the fast end.
7. 7
   Check the actual rise time with 1.5 k: t = 0.847 x 1500 x 150e-12 = 191 ns. Within the 300 ns limit with 36% margin.
8. 8
   Check the sink current with 1.5 k: 3.3 / 1500 = 2.2 mA. Within the 3 mA the devices must sink, so VOL will be comfortably below 0.4 V.
9. 9
   The 1.8 V side sees less capacitance (fewer devices) — say 60 pF. R_max = 300e-9 / (0.847 x 60e-12) = 5900 ohm. R_min = 467 ohm. Choose 2.2 k.
10. 10
    Static power: the bus is low roughly half the time during transfers. Average current on the 3.3 V side ~ 1.1 mA per line, so 2.2 mA for SDA and SCL together. On a battery-powered design this is significant and argues for larger pull-ups plus a slower bus, or for powering the bus down between transactions.
11. 11
    Finally check the level shifter does not break the timing: the MOSFET's body diode pulls the low side down when the high side is driven low, and the pull-ups do the rising edges. The rise time on the low-voltage side is what you calculated; the MOSFET adds a little capacitance. Add 10-20% margin.

Answer1.5 k to 3.3 V and 2.2 k to 1.8 V, with a low-threshold N-channel MOSFET per line as the bidirectional shifter. Rise time 191 ns against a 300 ns limit; sink current 2.2 mA against a 3 mA capability. Both the minimum and the maximum came from datasheet numbers, not from a rule of thumb.

Tool: ngspice plus PulseView on real hardware

• Simulate first. Create i2c_rise.cir modelling one line: a pull-up resistor to 3.3 V, a lumped bus capacitance to ground, and a switch to ground representing the open-drain driver.

• I2C rise time
  V1 vdd 0 DC 3.3
  Rpu vdd sda 1.5k
  Cbus sda 0 150p
  S1 sda 0 g 0 SW
  Vg g 0 PULSE(0 3.3 1u 1n 1n 1u 4u)
  .model SW SW(Ron=20 Roff=1e9 Vt=1.65)
  .tran 10n 10u
  .end

• Run and plot v(sda). Measure the 30% to 70% rise time with: meas tran trise TRIG v(sda) VAL=0.99 RISE=1 TARG v(sda) VAL=2.31 RISE=1
• Compare to your hand calculation of 191 ns. They should agree closely.
• Sweep the pull-up: change Rpu to 4.7 k and re-measure. Confirm the rise time scales linearly and now violates the 300 ns limit — this is the failure mode of the common 'just use 4.7 k' advice on a heavily loaded bus.
• Now measure reality. Connect a logic analyser or scope to a real I2C bus. A scope is essential here — a logic analyser reduces the signal to ones and zeros and will hide the slow rise entirely.
• Capture SCL and SDA rising edges and measure the actual rise time with cursors. Compare against your simulation and against the 300 ns spec.
• Add a device to the bus (or a length of wire) and re-measure. Observe the rise time lengthen as capacitance increases. Estimate the added capacitance from the change in rise time.

• NXP UM10204 - I2C-bus specification and user manualfreedoc~90 minThe authoritative free specification. Read section 7 (electrical specifications) and the pull-up sizing appendix. This is where the 300 ns and 3 mA numbers come from.
• TI Little Logic Guide - families, thresholds and translatorsfreereference~60 minFree guide covering logic families, thresholds and level translation options. The direction/speed/drive-type decision tree is the useful part.
• TI SCEA035B - Selecting the Right Level-Translation Solutionfreereference~45 minFree PDF covering the whole decision tree: direction, speed, drive type, and when a resistor divider, a MOSFET or a dedicated translator is correct. Read it alongside the I2C specification's own pull-up guidance.
• 74HC and 74LVC family datasheetsfreedatasheet~45 minPull a 74HC00 and a 74LVC00 datasheet and compare their VIH, VIL, VOH and VOL tables across supply voltage. Compute the noise margins for a 3.3 V to 5 V interface in both directions.

Design and verify the complete interface layer for a mixed-voltage system: a 3.3 V microcontroller connecting to a 5 V push-pull peripheral, a 1.8 V I2C sensor, and a 5 V open-drain interrupt line, plus one signal you must prove is safe without any shifter.

Deliverables

• A compatibility matrix: for every interface, a table with driver VOH(min)/VOL(max), receiver VIH(min)/VIL(max), the computed noise margins in both logic states, and a pass/fail verdict, with every number cited from a real datasheet.
• A level-shift decision per interface, naming the technique (divider, MOSFET, dedicated IC, or none needed) and the real part number where a part is used, with the reason it was chosen over the alternatives.
• I2C pull-up sizing worked in full for the 1.8 V bus: R_min from sink capability, R_max from rise time and estimated bus capacitance, the chosen E24 value, and the resulting rise time and static current.
• An ngspice simulation of the I2C rise time confirming the calculation, plus a second run at a deliberately wrong pull-up value showing the specification violation.
• A 5 V tolerance analysis for every 3.3 V input that could see 5 V: cite the datasheet's absolute maximum input voltage and its 5 V tolerance statement, and if the part is not tolerant, specify the protection.
• An unused-pin plan: every unused input on every device in the design tied high or low, with the method (direct or via resistor) and the reason stated.
• If you have the hardware, a measured rise-time capture on a real bus compared against the simulation.

Acceptance criteria — how you know it is good enough

• Every compatibility verdict is supported by four real datasheet numbers, not by 'they're both 3.3 V'.
• Noise margins are computed and any margin under 200 mV is flagged as a risk.
• The pull-up window is derived from both the sink and the rise-time constraints, and the chosen value is inside it with margin.
• 5 V tolerance is verified from datasheets, never assumed.
• Every unused input in the design is accounted for.
• The simulation agrees with the hand calculation within 10%.

If you want to push further

• Add bus capacitance measurement: estimate the bus capacitance from a measured rise time and a known pull-up, then verify by adding a known capacitor.
• Design the same interface set for a battery-powered device where static pull-up current matters, and quantify the energy saved by your changes over a day of operation.

• I verify level compatibility from VOH/VOL/VIH/VIL, in both directions, with real datasheet numbers.
• I compute noise margins and treat small margins as design risks.
• I know when a 3.3 V output can drive a 5 V input and when it cannot, and why the answer depends on family.
• I can size an open-drain pull-up from both the sink-current and rise-time constraints.
• I choose a level-shifting technique from direction, speed and drive type.
• I never leave a CMOS input floating, and I verify 5 V tolerance rather than assuming it.