Microcontroller Hardware Design

• The minimum systemEvery microcontroller needs the same five things: valid power on every supply pin, decoupling close to each of them, a clock (internal or external), a defined reset, and a way to get code in. Everything else is application. Getting these five right is the difference between a board that enumerates and a board that is a paperweight.
• Every supply pin is a supply pinModern parts have separate VDD, VDDA (analogue), VDDIO (bank supplies) and sometimes VDDCORE. Leaving one unconnected because 'it's probably internal' is a common and fatal error. The reference manual's power supply scheme diagram is mandatory reading, and analogue supplies usually need their own filtering.
• Decoupling: one per pin, close, smallEach supply pin gets its own 100 nF as physically close as the layout allows, plus bulk capacitance per rail. The loop area from the capacitor through the pin and back through ground is what determines effectiveness — a perfect capacitor 10 mm away with a via detour is worse than a mediocre one 1 mm away.100 nF per supply pin, 0402 or 0603, within a few millimetres, with the shortest possible ground return.
• Boot mode and strapping pinsMany parts sample specific pins at reset to decide where to boot from. These pins are often also GPIOs afterwards. If your application circuit holds a strapping pin the wrong way at reset, the chip boots into the wrong mode and nothing works. The reference manual lists them; put resistors on them and check every one.
• Debug and programming accessSWD (two pins plus reset), JTAG (four or five), or a bootloader over UART/USB. Bring the debug pins to a connector on every board, including production ones. The cost is a footprint; the cost of not having it is unbounded. Keep the debug traces short and avoid loading them with application circuitry.
• GPIO capability is not uniformPins differ in drive strength, 5 V tolerance, analogue capability, whether they can wake the part, and which peripheral functions they can be muxed to. Pin assignment is a real design task best done with the vendor's pin-planning tool before layout, because changing it after routing is expensive.
• Analogue supply and referenceVDDA typically needs a ferrite bead or small RC from the digital rail plus its own bulk and bypass capacitors. VREF may be the analogue supply or a separate precision reference, and the ADC's accuracy is limited by whichever you choose. Star-connect analogue ground to digital ground at a single sensible point, or use a solid plane and control the return paths.
• Unused pins, and pins that must not floatUnused GPIOs can be left floating only if firmware configures them as inputs with pull-ups enabled, and that is not true during reset. Safer to tie them or configure them as outputs early. Pins with special functions (USB D+/D-, oscillator pins, analogue references) have their own rules.

ProblemYou are handed a minimal RP2040 board schematic. Check it against the vendor's hardware design document and find what is missing.

1. 1
   Power pins: RP2040 has IOVDD (x6), DVDD (x2), VREG_VIN, VREG_VOUT, ADC_AVDD, USB_VDD. Confirm every one is connected. A schematic that connects 'VDD' as a single net has almost certainly missed the core/IO distinction.
2. 2
   The internal regulator: VREG_VIN takes 3.3 V and VREG_VOUT produces 1.1 V for DVDD. It needs a specific output capacitor value from the datasheet. Confirm VREG_VOUT is tied to both DVDD pins and that the capacitor is present and correct.
3. 3
   Decoupling: 100 nF per IOVDD pin (six of them), per DVDD pin (two), on ADC_AVDD and USB_VDD, plus bulk. Count the capacitors in the schematic against the pin count. Six IOVDD pins with two capacitors is a fail.
4. 4
   ADC_AVDD: the hardware design guide specifies a filter from 3.3 V (typically a ferrite bead or a small resistor plus capacitors). A direct connection to the digital rail costs you ADC bits.
5. 5
   Flash: the RP2040 has no internal program flash and boots from external QSPI flash. Confirm the flash is present, its CS is on the correct pin, and that the QSPI traces are short. Confirm the flash's supply and decoupling.
6. 6
   Crystal: 12 MHz crystal with the specified load capacitors, plus the series resistor the design guide calls for on XOUT. Check the crystal's CL against the fitted capacitors and the stray estimate.
7. 7
   Reset: RUN pin with a pull-up and optionally a button and a capacitor. Check the capacitor value against the required reset timing, and confirm the debug probe can also drive it.
8. 8
   Boot mode: the RP2040 boots to USB mass storage if the flash CS is held low at power-up. That is what the BOOTSEL button does — it pulls the flash CS low through a resistor. Confirm the button and its series resistor are present, and that the resistor value does not disturb normal QSPI operation.
9. 9
   Debug: SWD (SWCLK, SWDIO) plus ground brought to a connector or at least test pads. Confirm present.
10. 10
    USB: D+ and D- with the specified 27 ohm series resistors, routed as a differential pair. Confirm the resistors and that no additional pull-up is fitted (the RP2040 handles this internally, unlike some parts).
11. 11
    Result: the two things most commonly missing from a minimal schematic are enough decoupling capacitors (one per pin, not one per rail) and the ADC_AVDD filter. Both are in the design guide and both are silently degrading rather than fatal, which is why they get skipped.

AnswerCheck against the vendor's hardware design document line by line: every supply pin connected and individually decoupled, the internal regulator's specific capacitor, the ADC supply filter, the boot-mode strapping circuit, crystal loading with its series resistor, and debug access. The two usual omissions are per-pin decoupling and the analogue supply filter.

Tool: KiCad schematic capture of a minimum MCU system

• Create a new KiCad project. In the schematic editor, set up the page: title block with board name, revision, date and author. Do this first; it is part of the deliverable.
• Place the MCU symbol. For a large part, use a multi-unit symbol (KiCad splits big packages into logical units: power, port A, port B, etc.) so the sheet stays readable.
• Place power symbols (+3V3, GND, and a separate +3V3A if you have an analogue rail). Use power symbols rather than drawing wires across the sheet — this is what makes a schematic reviewable.
• Add decoupling: place one 100 nF per supply pin, drawn physically next to that pin on the schematic. Drawing them in a row at the edge of the sheet is common and makes the layout engineer's job harder. Place them where they belong.
• Add the crystal circuit with its load capacitors and any series resistor, labelled with the crystal's CL in a text note.
• Add the reset circuit and the debug connector. Use a real connector symbol with the correct pinout for your debug probe.
• Add strapping/boot pins with their resistors, and add a text note next to each explaining what it selects.
• Annotate the schematic (Tools > Annotate) and run ERC (Inspect > Electrical Rules Checker). Fix every error and every warning, or explicitly suppress a warning with a documented reason.
• Add a 'design notes' text block on the sheet listing the reference manual sections you checked against, with their numbers.
• Assign footprints to every symbol (Tools > Assign Footprints), choosing hand-solder variants if you will assemble it yourself.
• Export a PDF of the schematic. Print it. Review it on paper with the reference manual open — errors visible on paper are invisible on screen.

• Hardware design with RP2040 (Raspberry Pi)freedoc~120 minAn unusually good, freely available hardware design guide with a complete minimal schematic and explicit justification for every component. Read it cover to cover; it is short.
• RP2040 datasheetfreedatasheet~90 minRead the power supplies chapter and the electrical characteristics. Cross-reference against the design guide.
• KiCad schematic editor manualopen licencedoc~90 minRead the sections on hierarchical sheets, power symbols, multi-unit symbols and ERC configuration.
• Open-hardware reference schematics (e.g. Raspberry Pi Pico, Adafruit, SparkFun designs)freereference~60 minRead production schematics from vendors who publish them. Compare their decoupling, protection and connector choices against your own and ask why they differ.

Draw a complete, ERC-clean, review-ready schematic for a minimum microcontroller system of your choice (RP2040, STM32, ESP32, ATSAMD or similar), with every design decision traced to a specific section of the vendor's documentation.

Deliverables

• A KiCad schematic with a completed title block, organised across sheets or units so no sheet is crowded, exported to PDF.
• A power tree diagram: every rail, its source, its voltage, its estimated maximum current (with the estimate justified per consumer), and its sequencing requirement.
• A supply pin audit table: every power pin on the device, the net it connects to, and the decoupling capacitor reference designator assigned to it. No pin without a capacitor.
• A traceability table: at least 15 design decisions (crystal capacitor values, reset capacitor, boot strap resistors, USB series resistors, analogue filter, pull-up values, etc.) each with the specific document and section number that justifies it.
• A pin assignment table produced with the vendor's pin planning tool or by hand from the datasheet's alternate function table, showing every used pin, its function, its 5 V tolerance, and any conflict you had to resolve.
• A clean ERC report with zero errors and every remaining warning individually justified in writing.
• Footprints assigned to every symbol, with the choice of hand-solder versus nominal density stated and justified.
• A self-review checklist you completed on paper, with at least three findings you fixed as a result.

Acceptance criteria — how you know it is good enough

• Every supply pin on the device is connected and has its own decoupling capacitor.
• The analogue supply, if present, is filtered and this is justified from documentation.
• Every strapping or boot-mode pin is identified and has a defined state at reset.
• Debug access is present and brought to a connector or test pads.
• ERC passes with zero errors and all warnings justified.
• The traceability table has at least 15 entries with real section numbers.
• The paper review produced real findings, documented.

If you want to push further

• Add USB with correct series resistors, ESD protection and a differential-pair net class, and document the impedance target.
• Add a second power rail with a supervisor enforcing the sequencing requirement, and draw the sequencing timing diagram.

• I can draw a minimum microcontroller system from the reference manual without copying a reference design.
• I connect and individually decouple every supply pin.
• I identify and control every strapping and boot-mode pin.
• I always include debug access.
• I filter and reference analogue supplies deliberately.
• I trace design decisions to specific document sections and can defend each one.
• I get to zero ERC errors and justify every remaining warning.