Clocking, Timing Budgets and Reset

• The timing budget equationFor any synchronous interface between two chips, the clock period must cover the driver's clock-to-output delay, the flight time on the board, the receiver's setup requirement, and the clock skew between them. Hold time is checked separately against the minimum, not the maximum, delays.T >= t_co(max) + t_flight(max) + t_su + t_skew. Hold: t_co(min) + t_flight(min) >= t_hold + t_skew.
• Skew and jitter are different problemsSkew is a static difference in clock arrival time between destinations, caused by trace length and buffer differences; it is fixable by matching lengths. Jitter is a cycle-to-cycle variation in the clock edge itself, caused by the oscillator and by supply noise; it is reduced by better sources and cleaner power, not by routing.
• Choosing a clock sourceAn RC or internal oscillator is cheap and imprecise (1-5%). A ceramic resonator is around 0.5%. A crystal with the chip's internal oscillator is 10-50 ppm. A packaged crystal oscillator (XO) supplies a ready-made clock and removes all the load-capacitance uncertainty. A TCXO holds ppm over temperature. Your interface's tolerance requirement picks the technology.UART needs better than about 2% total error. USB full speed needs 0.25%. Ethernet needs 50 ppm. CAN needs a crystal.
• Crystal load capacitance and negative resistanceA crystal oscillates at its specified frequency only when it sees its specified load capacitance, which you create with two capacitors and the pin/stray capacitance. Get this wrong and the frequency is off, or the oscillator fails to start at temperature extremes. The oscillator circuit must also have enough negative resistance margin (typically 5x the crystal's ESR).CL = (C1 x C2)/(C1 + C2) + C_stray. C_stray is typically 2-5 pF and must be included.
• Propagation delay on a PCBSignals travel at roughly 6 inches (150 mm) per nanosecond on outer-layer microstrip and a bit slower on inner-layer stripline. For most low-speed designs this is negligible, but for a source-synchronous bus at 100 MHz+ it becomes a significant fraction of the budget and drives length matching.Microstrip: ~150 ps/inch (~6 ps/mm). Stripline: ~180 ps/inch (~7 ps/mm).
• Power-on reset and supply sequencingA microcontroller must be held in reset until its supply is valid and its clock is stable. Many multi-rail devices additionally require rails to come up in a specified order, with a maximum time between them. Violating a sequencing requirement can cause latch-up or excessive current, not merely a failure to boot.
• Brown-out detectionA slowly falling or sagging supply takes the processor through a region where it runs but computes wrongly, potentially corrupting non-volatile memory. A brown-out detector holds reset asserted below a threshold. Use the internal BOD if the part has one and its threshold is adequate; add an external supervisor if not.
• Reset topology on a boardOne reset source, distributed to everything that needs it, with the correct polarity and the correct release order. Reset lines are usually open-drain so that the supervisor, the debug probe and a button can all assert them. A reset that is only 100 ns long because someone used a small capacitor is a classic intermittent-boot bug.

ProblemA microcontroller drives a SPI flash. MCU t_co(max) = 8 ns after the SCK edge. Flash requires t_setup = 5 ns and t_hold = 5 ns. Trace lengths are 40 mm for SCK and 60 mm for MOSI, both on outer layers. Can you run 50 MHz?

1. 1
   50 MHz means a 20 ns period. SPI mode 0 launches data on one edge and captures on the next, so the available window is half a period = 10 ns.
2. 2
   Flight times: SCK at 40 mm x 6 ps/mm = 240 ps. MOSI at 60 mm x 6 ps/mm = 360 ps.
3. 3
   Setup check: the data must arrive at the flash's pin at least 5 ns before the clock edge arrives at the flash's pin.
4. 4
   Data arrives at: t_co(max) + t_flight(MOSI) = 8 + 0.36 = 8.36 ns after the launching clock edge at the MCU.
5. 5
   The capturing clock edge arrives at the flash at: 10 ns (half period) + t_flight(SCK) = 10 + 0.24 = 10.24 ns after the launching edge.
6. 6
   Setup margin = 10.24 - 8.36 - 5 = -3.12 ns. NEGATIVE. The interface fails setup at 50 MHz.
7. 7
   Find the maximum frequency: we need half_period + 0.24 - 8.36 >= 5, so half_period >= 13.12 ns, period >= 26.24 ns, f_max = 38 MHz. Round down to a standard divider: 33 MHz or 25 MHz.
8. 8
   Hold check at the lower frequency: data changes at t_co(min) + t_flight(MOSI). If t_co(min) is 2 ns, data changes at 2.36 ns after the launching edge. The previous capture edge arrived at 0.24 ns. Hold margin = 2.36 - 0.24 - 5 = -2.88 ns. Also negative!
9. 9
   Hold violations are not fixed by slowing the clock — the equation has no frequency term. The fixes are: lengthen the data trace, shorten the clock trace, or use a device with a larger t_co(min). Here, adding 30 mm to MOSI adds 180 ps — not nearly enough.
10. 10
    Re-read the datasheets. Often t_co(min) is not specified, in which case you must assume zero and this analysis says the interface cannot meet hold at any frequency — which is obviously false in practice. That is the signal that you are misreading the timing model: SPI mode 0 launches on the falling edge and captures on the rising edge, so the hold check spans half a period too, not zero. Redo it with the correct edges.
11. 11
    Corrected hold check: the capture edge of interest is a full half-period before the next data change. Hold margin = 10 + 2.36 - 0.24 - 5 = 7.12 ns. Passes comfortably.
12. 12
    Lesson: the arithmetic is easy; identifying which edges launch and which capture is where the errors are. Draw the waveform with both chips' timing diagrams side by side before writing any equations.

AnswerNo at 50 MHz — setup margin is -3.1 ns. Maximum is about 38 MHz, so run at 33 MHz or 25 MHz. And always draw the launch/capture edges from both datasheets' timing diagrams before computing; the edge relationship, not the arithmetic, is where timing analyses go wrong.

Tool: KiCad length tuning and the PCB Calculator, plus a spreadsheet timing budget

• Build a spreadsheet with columns: signal, driver t_co(min), driver t_co(max), trace length, propagation delay per mm, flight time, receiver t_setup, receiver t_hold, clock skew, setup margin, hold margin.
• Fill it for the SPI example above and confirm it reproduces the worked example's numbers. Make the clock period a single input cell so you can solve for f_max by changing one number.
• In KiCad's PCB editor, open the PCB Calculator's 'Transmission Line' tab. Enter a microstrip geometry (trace width, dielectric height, Er = 4.3 for FR-4) and read off the propagation delay per unit length. Compare to the 6 ps/mm rule of thumb.
• In a KiCad board, route two traces of deliberately different lengths. Use the 'Measure' tool or the net inspector to read their lengths.
• Use Route > Tune Length on the shorter trace to add a serpentine and match it to the longer one. Set a target length in the tuning settings and watch the live readout.
• Set up a length-matching design rule: in Board Setup > Design Rules, define a rule constraining the skew within a net class. Run DRC and confirm it flags an unmatched pair.
• Feed the tuned lengths back into your spreadsheet and observe the margin change.
• Finally, use the calculator's 'RF Attenuators'/'E-Series' tabs to size the crystal load capacitors for a specified CL, remembering to subtract stray capacitance.

• Crystal oscillator design application notes (any MCU vendor)freereference~90 minAN2867 is the best free treatment of crystal load capacitance, gain margin and negative resistance. Applies well beyond the vendor's own parts.
• KiCad PCB Calculator - transmission line and track widthopen licencetool~30 minFree and open. Use for propagation delay, impedance and track width.
• Any SPI flash and any MCU datasheet, timing sectionsfreedatasheet~60 minPull the AC characteristics tables and timing diagrams from both ends of a real interface. Practice identifying which edge launches and which captures.
• Power supply sequencing and supervisor app notesfreereference~45 minSearch for 'power supply sequencing' and 'microprocessor supervisor'. Covers reset thresholds, timeout selection and brown-out behaviour.

Produce the complete clocking, timing and reset design for a real board: a microcontroller with an external crystal, a SPI flash, an I2C sensor and a UART link to a host, plus a power supervisor.

Deliverables

• A timing budget spreadsheet for the SPI interface at your target frequency, with every value cited from a real datasheet, both setup and hold margins computed, and the maximum achievable frequency solved for.
• A drawn timing diagram showing which edges launch and which capture, annotated with the delays, produced before the arithmetic.
• A clock source selection: state the accuracy requirement of your most demanding interface (compute the UART budget explicitly: baud rate error tolerance for an 8N1 frame), then choose crystal, resonator or oscillator with the ppm figure that satisfies it.
• A crystal load capacitor calculation: the crystal's specified CL, your assumed stray capacitance, and the resulting C1 and C2 values in E-series terms, plus a check of the drive level and the series resistor if used.
• A reset design: the supervisor part chosen with its threshold and timeout, the reset topology (which devices, what polarity, open-drain or push-pull), the debug-probe and button connections, and the resulting reset pulse width.
• A power-up sequence diagram showing rail voltages against time, the reset release point, and evidence from each device's datasheet that its sequencing requirement is met.
• A brown-out analysis: the voltage below which your MCU misbehaves, the threshold you have set, and what protects non-volatile memory during a slow supply decay.

Acceptance criteria — how you know it is good enough

• Setup and hold are both computed, and the analysis identifies the correct launch and capture edges (a timing diagram is present and correct).
• The UART accuracy budget is computed from the frame length, not assumed.
• Crystal load capacitors account for stray capacitance and result in E-series values.
• The reset pulse width is computed and exceeds every device's minimum reset requirement.
• Sequencing requirements are cited from datasheets for every multi-rail device.
• The brown-out threshold is above the MCU's minimum operating voltage with margin, and below the regulator's minimum output.

If you want to push further

• Add a second clock domain (e.g. an audio codec on its own oscillator) and design the domain crossing, including the FIFO or handshake and the synchroniser.
• Measure a real crystal's startup time and drive level on hardware and compare to the vendor's negative-resistance guidance.

• I can build a setup and hold budget for an interface from two datasheets.
• I draw the launch and capture edges before doing timing arithmetic.
• I know that hold violations are not fixed by slowing the clock.
• I can compute crystal load capacitors including stray capacitance.
• I select a clock source from a computed accuracy requirement, not by habit.
• I design reset with a supervisor, correct polarity, adequate pulse width and verified sequencing.
• I can explain what brown-out detection protects against.