KiCad Projects and Schematic Capture

• A schematic is a communication document firstIt is read by reviewers, by the layout engineer, by the firmware engineer, and by you in two years. Signal flow left to right, power at the top, ground at the bottom, related circuitry grouped, no crossing wires where a label would do. A correct but unreadable schematic causes real errors downstream.
• Project structure and what to version controlA KiCad project is a folder: .kicad_pro, .kicad_sch, .kicad_pcb, plus project-local libraries and output directories. Commit the source files and the library tables; ignore generated outputs and backups. KiCad's file formats are text, so diffs and merges are meaningful — treat hardware like software.Version control: commit .kicad_pro, .kicad_sch, .kicad_pcb, .kicad_sym, .kicad_mod, *-lib-table. Ignore *-backups/, fp-info-cache, generated gerbers.
• Hierarchical sheetsBreak a design into sheets by function — power, MCU, sensors, connectors — with hierarchical labels carrying signals between them. This keeps each sheet reviewable, makes reuse possible, and lets several people work on one design. Flat single-sheet designs stop scaling at about 60 components.
• Labels: local, global and hierarchicalA local label connects within one sheet. A hierarchical label connects to the parent sheet's pin. A global label connects everywhere in the design and should be used sparingly — usually only for power and a handful of system-wide signals. Overusing global labels destroys the value of the hierarchy.
• Power symbols and the invisible power net trapPower symbols create nets by name, and any two symbols with the same name connect regardless of where they are. This is powerful and dangerous: a +3V3 symbol accidentally used on the pre-regulator side shorts your input to your output, and it looks fine on the page. ERC catches some of this; careful naming catches the rest.
• Net classesAssign nets to classes (power, high-speed, differential, default) in the schematic, and the layout inherits the trace widths, clearances and via sizes for each class. Doing this at schematic time rather than during routing is what makes a layout consistent and reviewable.
• ERC and what its warnings meanThe Electrical Rules Checker finds unconnected pins, conflicting outputs, missing power flags and unresolved labels. Getting to zero errors is mandatory. Getting to zero warnings is usually impossible and not the goal; the goal is that every remaining warning has been read and consciously accepted, ideally with an ERC exclusion carrying a comment.
• Annotation, designators and the layout handoffAnnotation assigns reference designators. Re-annotating after layout has started scrambles the association between schematic symbols and placed footprints, so annotate deliberately and then leave it alone. In modern KiCad the schematic and board are directly linked; 'Update PCB from Schematic' is the handoff, and it should be run and reviewed rather than trusted blindly.

ProblemYou have a design with a microcontroller, three sensors, a buck converter, an LDO, USB, and a connector. How should the schematic be organised?

1. 1
   Sheet 1 (root): a block diagram of the whole board as sheet symbols, with the inter-sheet signals visible as hierarchical connections. A reviewer should understand the architecture from this page alone.
2. 2
   Sheet 2 (Power): input protection, the buck, the LDOs, the power sequencing, and the power tree annotated with rail names and maximum currents as text. All power symbols defined here.
3. 3
   Sheet 3 (MCU): the microcontroller with its decoupling drawn adjacent to each supply pin, crystal, reset, boot straps, debug connector. Hierarchical labels out for every peripheral bus.
4. 4
   Sheet 4 (Sensors): the three sensors, their decoupling, their I2C addresses noted in text, their interrupt lines. Hierarchical labels in for I2C and out for interrupts.
5. 5
   Sheet 5 (Connectors and USB): the external connector with its protection, USB with series resistors and ESD, and the test points.
6. 6
   Naming: use a consistent convention. Rails as +3V3, +3V3A, +1V8, GND, GNDA. Buses as I2C1_SCL, I2C1_SDA. Active-low as RESET_N or nRESET, but pick one and never mix.
7. 7
   Global labels only for: GND and the power rails (via power symbols), and perhaps a system-wide RESET_N. Everything else crosses sheets through hierarchical pins so the connection is visible on the root sheet.
8. 8
   Net classes defined before layout: POWER (0.5 mm minimum width), USB (differential, 90 ohm), I2C (default), HIGH_CURRENT (1.5 mm), DEFAULT.
9. 9
   Text annotations that are worth their space: the I2C address of each device, the expected voltage on each rail, the crystal's CL, the reason for each strapping resistor, and a revision history block.
10. 10
    Run ERC. Add PWR_FLAG symbols where a net is driven by a source KiCad cannot recognise (a connector pin, a regulator output modelled as passive). Read every warning and either fix it or add a documented exclusion.
11. 11
    Review on paper. Print the whole thing, sit somewhere without a computer, and trace every net of the MCU against the datasheet's pinout. This finds errors that screen review does not.

AnswerFive sheets organised by function, a root sheet that is a readable block diagram, hierarchical pins for inter-sheet signals, global labels reserved for power, net classes defined before layout, and a paper review against the datasheet. The structure is the deliverable as much as the connectivity.

Tool: KiCad 9 schematic editor with git

• Create the project folder and run: git init. Add a .gitignore containing: *-backups/, fp-info-cache, *.kicad_prl, /gerbers/, /production/.
• In KiCad, File > New Project inside that folder. Commit the initial empty project so you have a baseline diff.
• Open the schematic editor. File > Page Settings: fill in title, company, revision, date and comments. Set a sensible sheet size (A3 is usually right for a dense sheet).
• Create hierarchical sheets: place a sheet symbol (Place > Sheet), name it and give it a filename, then double-click to enter it.
• Inside a sheet, place hierarchical labels (Place > Hierarchical Label) for signals crossing the boundary. Return to the parent and use Place > Import Sheet Pin to bring them onto the sheet symbol.
• Set up project-local libraries: Preferences > Manage Symbol Libraries > Project Specific Libraries. Add a project library so custom symbols travel with the project rather than living only on your machine.
• Define net classes: File > Schematic Setup > Net Classes. Create the classes and assign nets by name or by pattern.
• Annotate: Tools > Annotate Schematic. Choose 'Sort by X position' or by sheet, and keep the choice consistent across the project's life.
• Run ERC: Inspect > Electrical Rules Checker. Work through every error. For legitimate warnings, right-click the marker and choose 'Exclude this violation', then add a note in the schematic text explaining why.
• Commit at each meaningful step. Then make a small change and run: git diff -- '*.kicad_sch'. Read the diff. Learning to read KiCad's text diffs makes design review dramatically more effective.
• Export: File > Plot to produce a PDF of all sheets, and File > Export > Netlist if you need one for an external tool.

• KiCad official documentation - Schematic Editoropen licencedoc~180 minRead the full schematic editor manual once. It is long but it is the reference you will return to constantly. Pay particular attention to hierarchical sheets and ERC.
• KiCad - Getting Started in KiCadopen licencedoc~120 minThe official tutorial. Work through it fully with your hands on the keyboard, not by reading.
• Contextual Electronics - Getting to Blinky (KiCad video series)freevideo~240 minA free, complete walkthrough of a small KiCad project from schematic to fabrication. Follow along building the same board.
• Version control for KiCad projectsopen licencereference~30 minKiCad's own repository and its documentation on file formats. Understanding that the files are text is what unlocks meaningful hardware code review.

Take the microcontroller schematic from an earlier skill and grow it into a complete, hierarchically organised, version-controlled multi-sheet design with power, sensors and connectors, ready for layout.

Deliverables

• A git repository with a sensible .gitignore, at least eight commits with meaningful messages showing the design's evolution, and no generated files committed.
• A hierarchical schematic of at least four sheets plus a root sheet that functions as a readable block diagram.
• A completed title block on every sheet with revision, date and author.
• A documented naming convention for rails, buses and active-low signals, applied consistently, stated in a text block on the root sheet.
• Net classes defined for at least four classes with their trace widths, clearances and via sizes, and every net assigned.
• An ERC report with zero errors, and every warning either fixed or excluded with a written justification visible in the schematic.
• A PDF export of all sheets.
• A design decisions text block on each sheet recording the non-obvious choices made there.
• A git diff of one meaningful change (e.g. changing a resistor value or adding a component) with a written explanation of what the diff shows, demonstrating you can review hardware changes as code.

Acceptance criteria — how you know it is good enough

• The root sheet is understandable as a block diagram without opening the child sheets.
• Global labels are used only for power and, at most, one or two system-wide signals.
• Every sheet is readable at print size: no crossing wire spaghetti, signal flow left to right.
• ERC reaches zero errors and all exclusions are justified in writing.
• The git history shows incremental work, not a single 'add files' commit.
• Net classes exist and are assigned before any layout work begins.

If you want to push further

• Set up KiBot in CI to generate the schematic PDF, BOM and ERC report automatically on every push, and fail the build on ERC errors.
• Reuse one sheet in a second project as a hierarchical sheet instance, and document what had to change to make it reusable.

• I structure schematics hierarchically by function with a block-diagram root sheet.
• I use hierarchical labels for inter-sheet signals and reserve global labels for power.
• I define net classes before layout, not during routing.
• I reach zero ERC errors and justify every exclusion in writing.
• I version control KiCad projects and can read a schematic diff.
• I annotate schematics with the information a reviewer needs, not just connectivity.