Symbols, Footprints and Library Management

• A footprint error is the most expensive kindA wrong resistor value is a rework. A wrong footprint is a scrapped board batch and a two-week delay. Footprints therefore deserve verification out of proportion to the time they take to draw: check against the datasheet's mechanical drawing, check against a printed 1:1 copy, and have someone else check too.
• Symbol design conventionsPins grouped by function, not by physical position: power at the top, ground at the bottom, inputs left, outputs right. Pin names from the datasheet, pin numbers matching the package. Electrical pin types set correctly, because ERC depends on them. Multi-unit symbols for large parts.
• Land pattern anatomyPad size and shape, pad spacing, courtyard (the keep-out that guarantees the part can be placed and inspected), silkscreen outline and pin-1 marker, assembly outline, and the 3D model anchor. Each has a purpose and each is checked by a different downstream process.
• IPC-7351 density levelsLevel M (most material) gives the largest pads: best for hand soldering, wave soldering and inspection. Level N (nominal) is the general-purpose default. Level L (least) is for high-density boards. Choose deliberately per project and per part, not by whatever the library happened to contain.
• Thermal pads and paste aperturesA QFN or DFN's exposed pad needs the copper, the solder mask opening and the paste aperture all specified separately. A full-size paste aperture floats the part on too much solder; the convention is to break it into an array of smaller apertures covering 50-80% of the area, plus thermal vias with their own tenting or plugging decision.
• The KiCad Library Convention (KLC)KiCad publishes a formal convention covering naming, pin ordering, grid alignment, silkscreen line widths, courtyard clearances and metadata. Following it makes your libraries interoperable with the official ones and makes review possible against an objective standard rather than taste.
• Library management and reproducibilityGlobal libraries live on your machine; project libraries live with the project. A design that depends on your personal global library cannot be built by anyone else. Either use project-local libraries or vendor everything into the repository — and either way, verify by cloning the repo into a fresh directory and opening it.
• 3D models and mechanical checkingA STEP model attached to each footprint lets you check clearances, connector accessibility and enclosure fit in the 3D viewer, and export the whole board to mechanical CAD. Models are widely available free from manufacturers and from open repositories.

ProblemA sensor comes in a 4x4 mm QFN-24 with 0.5 mm pitch and an exposed thermal pad. There is no library part. Derive the land pattern.

1. 1
   Find the package drawing in the datasheet. Record: body size (4.00 mm nominal), pitch (0.50 mm), terminal width b (0.20-0.30 mm), terminal length L (0.35-0.45 mm), and the exposed pad size (2.60 x 2.60 mm typical).
2. 2
   Check whether the manufacturer publishes a recommended land pattern. Most do, usually in the package section or a separate application note. If so, use it as the primary source — the manufacturer has tested it.
3. 3
   If deriving from IPC-7351: pad width = terminal width max + a fabrication allowance. For a nominal density level, pad width is typically terminal width max plus about 0.05 mm, so 0.30 + 0.05 = 0.35 mm.
4. 4
   Pad length: the terminal length plus a toe extension outward and a heel extension inward. For QFN with nominal density, a common result is a pad length of about 0.75 mm, extending roughly 0.20 mm outside the body edge.
5. 5
   Pad spacing: pitch is fixed at 0.50 mm, so pad centres sit at 0.25, 0.75, 1.25 mm from the package centreline. Confirm 6 pads per side x 4 sides = 24.
6. 6
   Thermal pad: copper matching the datasheet's exposed pad, 2.60 x 2.60 mm. Do not oversize it — solder can wick and float the part.
7. 7
   Paste on the thermal pad: do not use a single 2.60 mm aperture. Use a 3x3 array of 0.75 mm squares with gaps, giving roughly 75% coverage. State the coverage percentage in the footprint's description.
8. 8
   Thermal vias: a 3x3 array of 0.3 mm drill vias in the thermal pad, connecting to an internal or bottom plane. Decide whether to tent them on the bottom side; untented vias under the pad wick solder away. Tent the bottom side, or use via-in-pad with filled and plated vias if the fab supports it.
9. 9
   Courtyard: the IPC courtyard excess for nominal density on this package class is typically 0.25 mm beyond the maximum extent of the pads and body. Draw it on the courtyard layer.
10. 10
    Silkscreen: an outline that does not overlap any pad (silkscreen on a pad prevents wetting and is a fab DRC violation), plus a pin-1 marker outside the courtyard so it remains visible after assembly.
11. 11
    Assembly layer: a full body outline plus the pin-1 indicator and the reference designator, for the assembly drawing.
12. 12
    Verify: print the footprint at exactly 1:1 scale on paper, place the real part on the printout, and check that every terminal sits inside its pad with even overhang. This costs one minute and catches scale, pitch and rotation errors that no amount of screen inspection will.
13. 13
    Verify again: check the pin numbering direction. QFN pin 1 is usually the lower-left when viewed from the top, numbering counter-clockwise. Getting this mirrored is a classic and fatal error — compare against the datasheet's top view explicitly, noting whether the datasheet shows a top or bottom view.

AnswerUse the manufacturer's recommended land pattern where published; otherwise derive from IPC-7351 nominal density. 0.35 x 0.75 mm pads on 0.50 mm pitch, a 2.60 mm thermal pad with a 75%-coverage paste array and nine tented thermal vias, a 0.25 mm courtyard, silkscreen clear of all pads, and a 1:1 paper check with the physical part before it is ever used.

Tool: KiCad Symbol Editor and Footprint Editor

• Read the KiCad Library Convention pages for symbols and footprints first. Keep them open.
• Symbol: open the Symbol Editor, create a project-local library, and add a new symbol. Set the reference prefix (U for ICs), the value, and add Datasheet, Manufacturer and MPN fields.
• Place pins on a 100 mil grid — KLC requires this and KiCad's wire snapping depends on it. Set each pin's electrical type: power input for supplies, output for driven pins, bidirectional for I/O, passive for things like crystal pins. ERC quality depends entirely on getting these right.
• Group pins by function. Use a multi-unit symbol if the part has more than about 30 pins.
• Footprint: open the Footprint Editor, create a project-local footprint library, and add a new footprint. Set the footprint's description and keywords.
• Use the pad array tool (Place > Add Pad, then Edit > Create Array) to place the four rows of a QFN accurately rather than by hand.
• Set pad properties: size, shape (roundrect with a small radius is standard for SMD), and for the thermal pad, use a custom pad or a separate paste aperture set via the pad's 'Custom shape' or by placing paste-only pads.
• Draw the courtyard on F.CrtYd with the correct line width (KLC specifies 0.05 mm), the silkscreen on F.Silkscreen (0.12 mm), and the assembly outline on F.Fab.
• Attach a 3D model: download the STEP file from the manufacturer, place it in a project 3d-models folder, and reference it with a relative path (using the ${KIPRJMOD} variable) so it resolves on other machines.
• Check it: use the Footprint Checker (in the Footprint Editor's Inspect menu) which validates against several KLC rules automatically.
• Print at 1:1: File > Print in the Footprint Editor, ensure the scale is exactly 1:1, and physically compare against the real part.
• Finally, clone your git repository into a fresh directory and open the project there. If any symbol or footprint fails to resolve, your library management is broken — fix it now, not when a colleague reports it.

• KiCad Library Convention (KLC)open licencedoc~90 minThe formal, objective standard for KiCad symbols and footprints. Read the symbol and footprint sections fully; use it as your review rubric.
• KiCad documentation - Symbol Editor and Footprint Editoropen licencedoc~120 minThe official manuals for both editors. Work through the tutorials with your hands on.
• IPC-7351 land pattern naming and density levelsfreereference~60 minFree calculator and documentation on land pattern generation. Understand the M/N/L density levels and the toe/heel/side fillet model.
• KiCad official libraries on GitLabopen licencereference~45 minRead the source of well-made footprints for packages similar to yours. The official libraries are the best worked examples available, and they are all open.

Create three complete library parts from scratch for components that are genuinely absent from the standard libraries, verify each one physically, and package them so another engineer can build your project.

Deliverables

• Three symbol/footprint pairs, each for a different package class: one fine-pitch IC with a thermal pad (QFN, DFN or a package with an exposed pad), one connector, and one mechanical or unusual part (a crystal, a switch, a module, or an inductor).
• For each part, the datasheet mechanical drawing with your derived dimensions annotated on it, showing pad size, pitch, courtyard and how each was derived.
• For the thermal-pad part: a paste aperture design with the coverage percentage stated, a thermal via plan, and a written statement of the tenting or plugging decision.
• A 1:1 print check for each footprint, photographed with the real part sitting on the printed pattern.
• Correct electrical pin types on every symbol pin, demonstrated by an ERC run on a test schematic that uses the parts and correctly flags a deliberate error (e.g. two outputs shorted).
• 3D models attached with relative paths, and a 3D viewer screenshot of a test board showing all three parts.
• A KLC compliance check: run KiCad's footprint checker and report the results, and manually check at least ten KLC rules that the automated checker does not cover, with a pass/fail for each.
• A reproducibility proof: a fresh clone of your repository opened on a clean path (or another machine) with every symbol, footprint and 3D model resolving, evidenced by a screenshot.
• A written pin-1 verification note for each part stating whether the datasheet drawing is a top or bottom view and how you confirmed the numbering direction.

Acceptance criteria — how you know it is good enough

• Every footprint's critical dimensions trace to a specific figure in the datasheet.
• The 1:1 physical check was done and is evidenced photographically.
• Pin-1 orientation is explicitly verified against a stated top-or-bottom view.
• Paste aperture coverage for the thermal pad is between 50% and 80% and is stated.
• Silkscreen does not overlap any pad on any footprint.
• Electrical pin types are correct, proven by ERC catching a deliberate error.
• The project opens cleanly from a fresh clone with no missing library references.

If you want to push further

• Write a script using KiCad's Python API to generate a family of footprints (e.g. all QFN sizes at a given pitch) programmatically, and validate the generated set.
• Contribute one of your footprints to the KiCad official libraries and address the review feedback you receive.

• I can derive a land pattern from a datasheet mechanical drawing and an IPC density level.
• I always verify a new footprint against the physical part at 1:1 scale.
• I verify pin-1 orientation against a stated top or bottom view.
• I design paste apertures and thermal vias for exposed-pad packages deliberately.
• I set electrical pin types correctly so ERC is meaningful.
• I manage libraries so a project builds from a fresh clone on another machine.
• I can review a footprint against the KiCad Library Convention.