Stackup Design and Component Placement

• Placement determines routing qualityBy the time you start routing, most of the outcome is already decided. Good placement makes routing nearly automatic; bad placement makes it impossible no matter how skilled the router. Budget serious time here and expect to redo it two or three times.
• Layer count is a requirements decisionTwo layers is cheap and adequate for slow, low-density designs, but has no continuous reference plane. Four layers gives you a ground plane, a power plane and two routing layers, and is the practical minimum for anything with a fast clock or a switching regulator. Six or more buys you more routing and better plane pairs. The cost difference between two and four layers at prototype quantities is usually small enough that four should be the default.
• Stackup: what goes next to whatSignal layers should be adjacent to a solid reference plane. Power and ground planes should be adjacent to each other with thin dielectric between, for PDN capacitance. A common 4-layer stackup is Signal / GND / PWR / Signal — but check the dielectric thicknesses: many default fab stackups put the two planes 1.2 mm apart, which wastes the plane capacitance entirely. Ask the fab for a stackup with the planes close together.A good 4-layer stackup: Sig / GND (0.2 mm) / PWR (thin core) / Sig. A bad one: Sig / GND / 1.2 mm / PWR / Sig.
• Impedance is a stackup propertyA 50 ohm single-ended or 90 ohm differential trace exists only in the context of a specific trace width, dielectric thickness and dielectric constant. You cannot specify impedance without specifying the stackup, and you must tell the fabricator that you require controlled impedance — it is a manufacturing option, not a default.
• Placement orderMechanically constrained parts first (connectors, mounting holes, anything that must line up with an enclosure). Then the parts with the tightest electrical constraints (switching regulator hot loop, crystal, decoupling). Then the parts with the most connections (the microcontroller, positioned and rotated to minimise crossings). Then everything else.
• Rotation is a free variable people forgetRotating the main IC by 90 degrees can eliminate dozens of crossings. So can swapping which side of it a connector sits on. Explore these before accepting a difficult routing problem — the ratsnest display shows you the answer directly.
• Grouping by function and by domainKeep each functional block together: the power stage in one region, the analogue front end in another, the digital core in a third. This localises return currents, limits coupling, and makes the board comprehensible. Analogue and digital sections should be adjacent to their own quiet regions of the ground plane rather than separated by a split.
• Thermal and mechanical placementHeat sources need copper area and should not sit under or next to temperature-sensitive parts (references, oscillators, sensors). Tall components need clearance from the enclosure lid. Connectors need mating clearance and strain relief. Mounting holes need keep-outs for screw heads and washers.
• Design for test and for reworkTest points on every rail and every critical signal. Fine-pitch parts need room to get a hot air nozzle in. Debug connectors need to be accessible with the board in its enclosure or fixture. These are placement decisions and they cannot be added later.

ProblemA 50 x 40 mm 4-layer board has a USB-C connector, a 5 V to 3.3 V buck, an RP2040-class MCU with QSPI flash and a crystal, a 24-bit ADC with a precision reference, and a screw terminal for the sensor input. Where does everything go?

1. 1
   Constraints first: the USB-C connector's position is fixed by the enclosure at the left edge. The screw terminal is fixed at the right edge. Four M2 mounting holes are at the corners with 3 mm keep-outs.
2. 2
   This immediately gives a natural left-to-right flow: power and digital on the left, analogue on the right. Signal flow and physical layout agree, which is the ideal case.
3. 3
   Buck converter: place it near the USB-C connector so the high-current input path is short. Orient the hot loop (input capacitors, IC, ground return) so it occupies the smallest possible area on the top layer, with the ground plane directly beneath on layer 2.
4. 4
   Critically: place the buck so its switch node and inductor are as far as practical from the ADC and its reference. Diagonal opposite corners if the board allows. Here, buck at bottom-left, ADC at top-right, roughly 55 mm apart.
5. 5
   MCU: centre-left, rotated so that its QSPI pins face the flash and its ADC/SPI pins face right toward the analogue section. Try both 0 and 90 degree rotations and compare the ratsnest crossing count.
6. 6
   QSPI flash: immediately adjacent to the MCU, on the same side, with the shortest possible traces. These are the fastest signals on the board.
7. 7
   Crystal: as close to the MCU's oscillator pins as physically possible, with its load capacitors adjacent and a local ground pour beneath. Keep it away from the buck's switch node and from any trace carrying fast edges.
8. 8
   Decoupling: one 100 nF per MCU supply pin, each placed against its pin with the via to the ground plane immediately adjacent to the capacitor pad, not at the end of a trace. This constrains placement of everything else around the MCU, so do it before placing the small stuff.
9. 9
   ADC and reference: top-right, grouped tightly. The reference's own decoupling next to it. The analogue input path from the screw terminal to the ADC kept short and away from digital traces.
10. 10
    Ground: a single unbroken ground plane on layer 2 across the whole board. Do not split it. Instead, control the return paths by keeping digital and analogue traces in their own regions — the return current follows the signal, so separated signals give separated returns automatically.
11. 11
    Test points: on 5 V, 3.3 V, 3.3 V analogue, the reference output, the switch node (for scoping the buck) and reset. Place them where a probe can reach with the board in a fixture.
12. 12
    Debug connector: accessible from the top with the board mounted. Place near the MCU with short SWD traces.
13. 13
    Thermal: the buck dissipates a few hundred milliwatts. Give it a copper pour on the top layer and thermal vias to the plane, and check nothing temperature-sensitive is within 10 mm downstream in the airflow.
14. 14
    Now check: display the ratsnest with everything placed and look for long lines that cross the board. Each one is a placement question. Iterate two or three times before routing anything.

AnswerMechanical constraints fix the ends; power and digital on the left, analogue on the right, buck and ADC diagonally opposed. Decoupling placed before general components. Unbroken ground plane on layer 2. Two or three placement iterations judged by ratsnest crossings, before any routing.

Tool: KiCad PCB editor: stackup, placement tools and the ratsnest

• Board Setup > Physical Stackup: set the layer count to 4. Enter the dielectric thicknesses. Get these from your chosen fabricator's published stackup table rather than accepting KiCad's defaults — fabricators publish these freely.
• Set the copper weight per layer (1 oz / 35 um outer is typical) and the dielectric constant (about 4.3 for standard FR-4 at low frequency, but your fab may specify differently).
• Board Setup > Board Editor Layers: name the layers meaningfully (F.Cu = 'Top signal', In1.Cu = 'GND', In2.Cu = 'PWR', B.Cu = 'Bottom signal').
• Use the PCB Calculator's Transmission Line tab with your stackup's dielectric thickness to find the trace width for 50 ohm single-ended and the width/gap for 90 ohm differential. Record these in your net class definitions.
• Draw the board outline on Edge.Cuts. Use a rectangle with rounded corners (fabricators prefer a minimum 1 mm corner radius) and place mounting holes with keep-out zones.
• Import the mechanical constraints: if you have a STEP model of the enclosure, use File > Import > Graphics or overlay it in the 3D viewer to check connector positions.
• Place the constrained parts first, using absolute coordinates typed into the properties dialog rather than dragging, so they are exactly where the mechanical drawing says.
• Turn on the ratsnest (it is on by default) and place the major ICs. Use the 'R' key to rotate and watch the ratsnest change. Try each orientation and note the visual crossing count.
• Use Edit > Move Exactly and the alignment tools (Align > Align to top/left, Distribute horizontally) to place rows of decoupling capacitors precisely.
• Use the 'Highlight net' feature to see a specific net's connections while placing.
• Once placed, run the 3D viewer and check heights against your enclosure, connector accessibility and mounting hole clearances.
• Take a screenshot of the ratsnest at each placement iteration so you can show the improvement.
• Finally, add a fabrication note on the User.Drawings or User.Comments layer stating the required stackup and that controlled impedance is required, with the target impedances and their nets.

• KiCad documentation - PCB Editor, board setup and stackupopen licencedoc~90 minRead the board setup, layer and design rules chapters before starting.
• Fabricator stackup tables (e.g. JLCPCB, OSH Park, Aisler capabilities pages)freereference~45 minFree and specific. Get the real dielectric thicknesses and impedance-controlled stackup options from the fab you actually intend to use. Designing to a generic stackup and then discovering your fab does not offer it is a common and avoidable delay.
• Rick Hartley and Eric Bogatin on stackup and plane pairsfreevideo~90 minThe stackup section of this talk explains why plane spacing matters and why the common default 4-layer stackup is poor. Free.
• Open hardware layouts to studyopen licencereference~90 minOpen KiCad projects on GitHub. Download several boards similar to yours and study their placement decisions. This is the closest thing to an apprenticeship available for free.

Produce a fully placed (not routed) 4-layer board from your existing schematic, with a documented stackup, a documented placement rationale, and evidence of iteration.

Deliverables

• A stackup specification: four layers with their assignments, dielectric thicknesses taken from a named fabricator's published stackup, copper weights, total board thickness, and the trace width and gap needed for your controlled-impedance nets, computed from that stackup.
• A board outline with mounting holes, keep-outs and any mechanical constraints, dimensioned on a User layer.
• A fully placed board with every component positioned and rotated, no overlaps, all courtyards clear, and DRC's courtyard check passing.
• A placement rationale document: for each functional block, why it is where it is, what constrained it, and what it is being kept away from. At least eight numbered decisions.
• Evidence of at least three placement iterations: ratsnest screenshots from each, with a written statement of what changed and why the later one is better (e.g. crossing count, longest ratsnest line length).
• A decoupling placement audit: a screenshot per supply pin group showing the capacitor position and its via arrangement, with the mounting loop described.
• A 3D render showing component heights, connector accessibility and mounting hardware clearance, with any interference identified and resolved.
• A thermal placement note: identify every part dissipating more than 100 mW, its copper allocation, and the nearest temperature-sensitive component with the separation distance.
• A test and rework access plan: the test points placed, and a statement of how each fine-pitch part would be reworked in place.
• A fabrication note on a drawing layer specifying the required stackup and impedance control.

Acceptance criteria — how you know it is good enough

• The stackup uses real dielectric thicknesses from a named fabricator, and the power and ground planes are adjacent with thin dielectric.
• Impedance-controlled trace geometry is computed from the actual stackup, not taken from a rule of thumb.
• Every decoupling capacitor is placed against its supply pin with a short, direct via to the plane.
• The switching regulator's hot loop is compact and its area is stated.
• Noise sources and sensitive circuits are physically separated with the distance stated.
• At least three placement iterations are evidenced with a stated improvement metric.
• The 3D check found and resolved at least one real mechanical issue.

If you want to push further

• Produce two complete alternative placements for the same schematic and evaluate them against a written scoring rubric (routing difficulty, thermal, noise separation, mechanical, testability).
• Export the board to STEP and check it against the enclosure model in FreeCAD, reporting the minimum clearance found.

• I choose layer count from requirements and can justify it.
• I configure stackups from a real fabricator's published options, with adjacent plane pairs.
• I compute controlled-impedance geometry from the actual stackup.
• I place mechanically constrained parts first, then electrically critical parts, then the rest.
• I place decoupling before general components.
• I iterate placement and judge it against the ratsnest before routing anything.
• I separate noise sources from sensitive circuits and can state the distances.
• I plan for test and rework access at placement time.