Routing and Trace Design

• Trace width comes from current and allowable temperature riseIPC-2152 relates current, cross-sectional area, copper weight, layer position and allowable temperature rise. Internal traces run hotter than external ones for the same current because they are surrounded by insulating dielectric. Never route power by eye.1 oz external copper: roughly 0.5 mm width per amp for a 10 C rise. Internal traces need roughly double.
• Vias have resistance, inductance and a current limitA via is a plated barrel with finite copper. For high-current paths, use several vias in parallel. For high-speed signals the via's inductance and its stub (the unused portion of the barrel on a multilayer board) matter, which is why back-drilling and blind vias exist. For most designs the practical rule is: more vias on power, fewer vias on fast signals.A 0.3 mm drill, 0.6 mm pad via carries roughly 1-1.5 A comfortably and adds around 0.5-1 nH.
• Layer discipline and reference continuityA trace's return current flows in the nearest reference plane. Changing layers changes the reference, and unless a stitching via connects the two references nearby, the return has to detour, creating a loop. Route fast signals so they stay on one layer, or place a ground via within a few millimetres of every layer change.
• Differential pairsTwo traces carrying equal and opposite signals. The differential impedance depends on both the trace geometry and their separation. They must be routed together, with matched lengths, symmetric routing, and no other signal between them. Breaking the coupling — routing them apart around an obstacle — converts differential energy to common mode, which is what radiates.
• Length matching and when it mattersMatching is required when the receiver samples several signals against a common clock and the skew budget is tight. Compute the actual budget first — matching a 100 kHz I2C bus is pure ritual, while matching a DDR byte lane to within 0.5 mm is essential. Use serpentines with adequate spacing between segments so they do not couple to themselves.Only match when your timing budget requires it. Compute the required tolerance in picoseconds, then convert to millimetres at ~6 ps/mm.
• Fanout and escape routingGetting signals out from under a fine-pitch BGA or QFN is a solved problem with standard patterns: dog-bone vias for BGAs, alternate-side escapes for QFNs. Doing this systematically at the start prevents the situation where the last twenty nets have nowhere to go.
• Angles, acid traps and manufacturabilityThe 45-degree convention is about manufacturability history and habit rather than electrical performance at most speeds, but acute angles do create acid traps in etching and should genuinely be avoided. Modern KiCad supports arcs and any-angle routing; use them where they help, but keep angles obtuse.
• Copper pours: helpful and harmfulA ground pour on a signal layer can improve shielding and thermal performance, but a poorly stitched pour creates floating copper islands that act as antennas, and a pour that necks down between components creates a poor return path that is worse than no pour. Stitch pours generously or do not use them.

ProblemA 5 V, 3 A rail runs 35 mm from a connector to a buck converter. USB 2.0 full speed runs 25 mm from a USB-C connector to the MCU. Design both routes.

1. 1
   Power path first. Requirement: 3 A, allowable temperature rise 10 C, 1 oz copper, external layer.
2. 2
   From the KiCad PCB Calculator's Track Width tab (IPC-2152 based): 3 A at 10 C rise on 1 oz external copper needs roughly 1.6 mm. Round up to 2.0 mm for margin and for the DC resistance benefit.
3. 3
   Check DC drop: 2.0 mm wide, 35 mm long, 1 oz (35 um) copper. Cross-section = 2.0e-3 x 35e-6 = 7.0e-8 m^2. Resistance = rho x L / A = 1.68e-8 x 0.035 / 7.0e-8 = 8.4 milliohm. Drop at 3 A = 25 mV. Acceptable for a 5 V rail.
4. 4
   If the route must change layers, use at least four parallel vias at each transition: 3 A / 1.2 A per via = 2.5, so three minimum, four for margin.
5. 5
   Return path: the ground return should run directly beneath on the plane, which it will do automatically if the plane is unbroken. Verify no plane split or large via array sits under the power route.
6. 6
   Now the USB pair. USB 2.0 full speed (12 Mbps) has slow enough edges that impedance control is not strictly mandatory over 25 mm, but doing it properly costs nothing and it is required for high speed (480 Mbps).
7. 7
   Target: 90 ohm differential. From the stackup (0.2 mm dielectric to the ground plane on layer 2, er = 4.3), the PCB Calculator's coupled microstrip tab gives approximately 0.30 mm trace width with 0.20 mm gap. Verify against your fabricator's impedance calculator, which accounts for their actual materials and etch compensation.
8. 8
   Route the pair together on the top layer, referenced to the unbroken ground plane on layer 2, for the whole 25 mm. No layer changes.
9. 9
   Keep the series resistors (if the part requires them) symmetric: both resistors at the same distance along the pair, placed side by side, with the pair spacing maintained through the resistor pads.
10. 10
    Length matching: USB full speed has an enormous skew budget; even so, match to within 1 mm because it costs nothing at this length. For USB high speed the requirement is typically under 0.15 mm.
11. 11
    Keep the pair at least 3x the dielectric height (0.6 mm) away from any other signal, and considerably further from the buck's switch node — aim for 5 mm or more, or route on the opposite side of the ground plane.
12. 12
    ESD protection: place the TVS array as close to the connector as possible, with the pair passing through it rather than stubbing off it. A stub to an ESD part is both an impedance discontinuity and a poor ESD path.
13. 13
    Finally, set both as net classes: POWER_3A with 2.0 mm width and a via count rule, and USB with the computed differential geometry and a length-matching rule. Then let DRC enforce what you decided.

AnswerPower: 2.0 mm trace, 8.4 milliohm, 25 mV drop, four vias per layer transition. USB: 0.30 mm traces with 0.20 mm gap for 90 ohm differential, routed together on one layer over unbroken ground, matched to 1 mm, TVS in-line at the connector, 5 mm minimum from the switch node. Both encoded as net classes so DRC enforces them.

Tool: KiCad interactive router, net classes and length tuning

• Board Setup > Net Classes: create classes for POWER, USB (differential), HIGHSPEED and DEFAULT. Set trace width, clearance, via size and drill for each. For USB, set the differential pair width and gap.
• Assign nets to classes by name pattern (e.g. all nets matching '+*' to POWER) or individually.
• Board Setup > Design Rules: add custom rules if needed. KiCad's rule language can express things like 'clearance from any net in class HIGHSPEED to the SWITCH_NODE net is at least 2 mm'. Write that rule now rather than remembering it later.
• Set the router mode: the interactive router has Highlight Collisions, Shove and Walk Around modes (cycle with the 'M' key while routing, or set in Preferences). Shove is usually the most productive; Walk Around is safer in dense areas.
• Route the power nets first, at their full width, taking the most direct path. Power routing constrains everything else, so do it before signals.
• For differential pairs, use the differential pair router tool (in the Route menu, or press '6'). It routes both traces together, maintaining the gap.
• Use Route > Tune Differential Pair Skew to equalise the two traces within the pair, and Route > Tune Track Length to match lengths between nets in a group. Set the target in the tuning settings dialog and watch the live readout.
• Place stitching vias: after routing, add ground vias near every layer transition of a fast signal and around the board perimeter. KiCad has a via stitching feature, or place them manually and use Edit > Create Array.
• Fill zones with 'B' and inspect the result. Look specifically for isolated copper islands and for necked-down regions where the pour has to squeeze between vias. KiCad's zone properties have an option to remove islands; use it, then check whether removing them left a return path broken.
• Run DRC (Inspect > Design Rules Checker) with 'Test for parity between PCB and schematic' enabled. Fix everything.
• Use Inspect > Net Inspector to review every net's routed length, via count and layer usage. Sort by length and check that nothing unexpected is long.
• Finally, turn on 'Show ratsnest for unrouted nets' and confirm the count is zero.

• KiCad documentation - interactive routing and length tuningopen licencedoc~120 minRead the routing chapter fully, including the differential pair and tuning tools and the custom design rule syntax.
• IPC-2152 based trace width calculators (KiCad PCB Calculator)open licencetool~30 minThe Track Width tab implements the current-carrying calculation. Free and open, and it is in the tool you are already using.
• Fabricator impedance calculators and stackup toolsfreetool~30 minFree vendor calculators using their actual materials and etch compensation. Always cross-check your geometry against the fab that will build the board.
• Phil's Lab - KiCad routing and high-speed design videosfreevideo~180 minFree, practical, KiCad-specific routing walkthroughs including differential pairs, impedance control and stackup. Watch a full board routing video start to finish.

Fully route the board you placed in the previous skill, with every routing constraint expressed as a design rule and enforced, and produce a routing report that justifies each decision numerically.

Deliverables

• A fully routed board with zero unrouted nets and zero DRC errors, including schematic-parity checking.
• A net class specification table: every class with its trace width, clearance, via size, and the calculation or requirement behind each number.
• A current-carrying analysis for every net carrying more than 500 mA: current, chosen width, resulting temperature rise from the IPC calculation, DC resistance, and voltage drop over the routed length.
• A via strategy: via sizes used, the current rating assumed per via, the via count at each high-current layer transition, and the stitching via placement rule you followed.
• For any controlled-impedance nets: the geometry, the calculator used, a cross-check against the fabricator's own impedance calculator, and the routed lengths and match tolerance achieved.
• A layer-transition audit for every fast signal: each layer change identified, with the nearest stitching via and its distance stated.
• At least two custom KiCad design rules written in the rule language (for example a keep-out from the switch node, or a differential skew constraint), with the rule text quoted and a screenshot of DRC catching a deliberate violation.
• A copper pour review: screenshots of every zone fill with any isolated islands identified and resolved, and a statement of how the pour is stitched.
• A Net Inspector export showing every net's length and via count, with the five longest nets explained.
• A routing self-review against a written checklist of at least twelve items, each evidenced.

Acceptance criteria — how you know it is good enough

• DRC passes with zero errors including schematic parity, and zero unrouted nets.
• Every trace width above 500 mA is justified by a current-carrying calculation, not chosen by eye.
• Controlled-impedance geometry is cross-checked against the fabricator's calculator.
• Every fast-signal layer transition has a stitching via within a stated distance.
• At least two custom design rules exist and are demonstrated to work.
• No copper islands remain, and pour continuity under critical signals is verified.
• The routing checklist has at least twelve items, each evidenced rather than asserted.

If you want to push further

• Route the same board on two layers instead of four and document every compromise forced by the loss of the ground plane.
• Add a second controlled-impedance interface (e.g. a 50 ohm single-ended RF trace or an LVDS pair) and verify the geometry with a field solver or the fabricator's calculator.

• I compute trace widths from current and temperature rise rather than choosing by eye.
• I size via counts for current and place stitching vias at layer transitions.
• I route differential pairs together with maintained coupling and matched lengths.
• I only length-match where a computed timing budget requires it.
• I express routing constraints as design rules so DRC enforces them.
• I check copper pours for islands and return-path continuity.
• I reach zero DRC errors including schematic parity.