Design Rules, DRC and Design Verification

• Design rules come from three placesThe fabricator's capability (minimum trace, minimum space, minimum drill, annular ring, mask sliver), the assembler's capability (minimum part spacing, courtyard, fiducials), and your own electrical requirements (creepage for voltage, impedance geometry, keep-outs). All three must be encoded, and only the first is commonly done.
• Capability versus costEvery fabricator publishes a standard capability set and a set of advanced options that cost more. Designing to 0.1 mm trace and space when your fab's standard is 0.15 mm turns a cheap board into an expensive one. Read the capability table and design to the standard tier unless you have a reason.
• Electrical clearance and creepageIPC-2221 gives minimum conductor spacing versus voltage, with different tables for coated and uncoated, internal and external. For mains or high voltage, creepage (across a surface) and clearance (through air) are separate requirements from a safety standard, and they drive slots and keep-outs in the board.
• Annular ring and drill-to-copperThe annular ring is the copper remaining around a drilled hole after registration tolerance. Too small and the drill can break out of the pad. Drill-to-copper is the minimum distance from a hole to unrelated copper. Both are fabrication limits that DRC must enforce, and both are common causes of a board being rejected at CAM review.
• Solder mask rulesMask expansion (how much larger the mask opening is than the pad) and mask sliver (the minimum width of mask between two openings). If the gap between fine-pitch pads is smaller than the fab's minimum sliver, the mask between them will not form and you get bridging. This is a real and frequently missed constraint on 0.4 mm pitch parts.
• DRC-clean is necessary, not sufficientDRC checks what you told it to check. It cannot know that you connected the crystal to the wrong pins, that your footprint is mirrored, or that the connector faces the wrong way. Verification therefore needs layers: automated DRC, automated parity checking against the schematic, gerber review in an independent viewer, 3D review, and human review against a checklist.
• Independent verification of outputsThe gerbers are what gets manufactured, not your design file. Always open the generated gerbers in a viewer that is not your EDA tool. Bugs in output generation are rare but catastrophic, and this check takes five minutes.
• Review checklists beat review vigilanceA written checklist finds errors that an experienced engineer looking carefully will miss, because attention is unreliable and lists are not. Build a personal checklist and add to it every time you find a bug — especially your own.

ProblemYou are using a 0.4 mm pitch QFN. Your fabricator's standard capability is 0.127 mm trace/space, 0.2 mm minimum drill, 0.05 mm minimum annular ring, 0.1 mm minimum mask sliver, 0.05 mm mask expansion. Will it manufacture?

1. 1
   Pad geometry: 0.4 mm pitch with a 0.2 mm pad width leaves 0.2 mm of space between adjacent pads.
2. 2
   Mask sliver check: the mask openings are pad size plus 2 x expansion = 0.2 + 0.1 = 0.3 mm wide. The remaining mask between them is 0.4 - 0.3 = 0.1 mm. That exactly equals the minimum sliver of 0.1 mm. Marginal — a small registration error and the mask disappears.
3. 3
   Mitigation: reduce the mask expansion to 0.025 mm for this footprint. Openings become 0.25 mm, slivers become 0.15 mm, with 50% margin. KiCad supports per-footprint and per-pad mask expansion overrides — set it on the footprint.
4. 4
   Alternatively, request a mask-defined (rather than copper-defined) pad arrangement, or accept a single mask opening covering the whole row and rely on the paste stencil and surface tension. Both are legitimate but must be a deliberate choice communicated to the fab.
5. 5
   Escape routing: can a 0.127 mm trace escape between two pads? The gap is 0.2 mm; a trace of 0.127 mm centred leaves 0.0365 mm clearance on each side. The fab's minimum space is 0.127 mm. FAILS.
6. 6
   So you cannot route between adjacent 0.4 mm pitch QFN pads at standard capability. The escape must be by via-in-pad, or by escaping the outer ring on the same layer and dropping vias outside the package, or by upgrading to a finer capability tier.
7. 7
   Practical answer for a QFN (as opposed to a BGA): all pads are on the perimeter, so route each pad outward radially and place its via outside the courtyard. No between-pad routing needed. The problem only becomes hard for BGAs with inner rows.
8. 8
   Via and annular ring: choose a 0.3 mm drill with a 0.6 mm pad, giving an annular ring of (0.6 - 0.3)/2 = 0.15 mm, comfortably above the 0.05 mm minimum.
9. 9
   Thermal pad vias: 0.3 mm drill vias in the thermal pad. Check drill-to-copper against the surrounding pads, and decide on tenting. Tent the bottom side to prevent solder wicking.
10. 10
    Now encode all of this: in Board Setup > Design Rules, set the global minimums to the fab's standard capability. Add a custom rule constraining the QFN's local mask expansion. Add a net class for the QFN's signals if their width differs.
11. 11
    Verify by generating gerbers and opening them in an independent viewer, zoomed in on the QFN, checking the mask openings and slivers visually at high magnification.

AnswerIt manufactures, but only with the mask expansion reduced to 0.025 mm for that footprint (default expansion produces a marginal 0.1 mm sliver) and with radial escape routing rather than routing between pads. Both constraints come from the fab's published table, and both are invisible unless you check.

Tool: KiCad design rules, the custom rule language, and an independent gerber viewer

• Download your chosen fabricator's capability table (they are all published free) and note: minimum trace, minimum space, minimum drill, minimum annular ring, minimum mask sliver, minimum mask expansion, minimum silk width, and minimum silk-to-mask clearance.
• In KiCad: Board Setup > Design Rules > Constraints. Enter the minimums. Set 'Minimum clearance', 'Minimum track width', 'Minimum annular width', 'Minimum via diameter', 'Minimum through hole', 'Hole to hole clearance' and 'Silk clearance'.
• Board Setup > Design Rules > Solder Mask/Paste: set the global mask expansion. Then override it on specific footprints via the footprint's properties.
• Board Setup > Design Rules > Custom Rules: this is a text editor for KiCad's rule language. Write a rule such as:

  (rule "HV clearance"
    (constraint clearance (min 1.5mm))
    (condition "A.NetClass == 'MAINS' && B.NetClass != 'MAINS'"))

  and

  (rule "keep signals off switch node"
    (constraint clearance (min 2mm))
    (condition "A.NetName == '/SW' && B.NetClass == 'DEFAULT'"))

• Run DRC (Inspect > Design Rules Checker) with all options enabled, including 'Test for parity between PCB and schematic' and 'Check for footprint courtyard overlap'.
• Deliberately violate one of your custom rules and confirm DRC catches it. An unverified rule is not a rule.
• Generate outputs: File > Fabrication Outputs > Gerbers, and Drill Files. Put them in a separate directory that is gitignored.
• Open the gerbers in an independent viewer — tracespace.io/view (open source, browser-based), or the open-source gerbv desktop application. Do not use KiCad's own gerber viewer for this check; the point is independence.
• In the viewer, check layer by layer: is the copper what you expect, is the mask opening where you expect, is the silkscreen clear of pads, is the drill file aligned with the copper, is the board outline closed?
• Zoom to the finest-pitch part and inspect the mask slivers visually.
• Check the drill file separately: confirm the hole count and sizes match your expectation, and that plated and non-plated holes are correctly separated.
• Finally, some fabricators offer a free DFM analysis on upload. Run it and read every warning, even if you intend to ignore some.

• KiCad documentation - design rules and the custom rule languageopen licencedoc~90 minThe custom rules reference is the important part. It is a genuinely powerful constraint language and almost nobody uses it.
• Fabricator capability tablesfreereference~30 minFree and specific. Download the capability table for the fab you will actually use, and design to their standard tier.
• tracespace gerber viewer (open source)open licencetoolBrowser-based, open-source gerber viewer. Use it for the independent output check. gerbv is the desktop equivalent.
• IPC-2221 conductor spacing, via the KiCad PCB Calculatorfreereference~30 minKiCad's PCB Calculator has an Electrical Spacing tab implementing the IPC-2221 tables. Use it for any design with voltages above about 30 V.

Produce a complete, documented verification package for your board: rules derived from a real fabricator, custom rules for your own requirements, and a multi-layer verification process with evidence at each stage.

Deliverables

• A design rule specification document: every constraint value, its source (fabricator capability table with the page or URL, assembler requirement, IPC table, or your own electrical requirement), and the KiCad setting where it is encoded.
• At least three custom KiCad design rules addressing requirements the built-in constraints cannot express, with the rule text quoted and each demonstrated to fire on a deliberate violation (screenshots).
• A clearance analysis for the highest voltage on the board using the IPC-2221 tables, with the required spacing and the actual minimum spacing achieved.
• A mask sliver check for the finest-pitch part: the pad geometry, the mask expansion, the resulting sliver width, and the fabricator's minimum, with any per-footprint override documented.
• A clean DRC report with zero errors, all checks enabled including schematic parity and courtyard overlap.
• An independent gerber review: screenshots from a non-KiCad viewer of every layer, with a written checklist confirming copper, mask, paste, silk, drill and outline are each correct.
• A drill file review: hole count and size table, with plated and non-plated correctly separated.
• A 3D review with at least four screenshots from different angles, checking component clearance, connector accessibility and mounting hardware.
• A personal design review checklist of at least twenty-five items, organised by category, with each item ticked and, where applicable, the evidence referenced. At least five items must be ones you added from your own past mistakes.
• A free DFM analysis report from a fabricator's upload tool, with every warning addressed or explicitly accepted with a reason.

Acceptance criteria — how you know it is good enough

• Every rule value traces to a named source, not to habit.
• At least three custom rules exist and are each demonstrated to fire.
• Mask sliver is computed for the finest-pitch part and meets the fab minimum with margin.
• The gerber review used a viewer independent of KiCad.
• DRC passes with all checks enabled, including schematic parity.
• The personal checklist has at least twenty-five items and includes items derived from real past errors.
• Every DFM warning is addressed or explicitly accepted with a written reason.

If you want to push further

• Automate the whole verification in CI with KiBot: DRC, ERC, gerber generation, and a diff against the previous revision's outputs, failing the build on any error.
• Write a script that parses the gerber files and independently measures the minimum trace and space, and compare its answer to KiCad's DRC.

• I derive design rules from a real fabricator's capability table, not from defaults.
• I encode my own electrical requirements as custom rules so DRC enforces them.
• I verify that a rule actually fires before trusting it.
• I check mask slivers on fine-pitch parts.
• I review generated gerbers in an independent viewer before ordering.
• I use a written checklist and add to it from my own mistakes.
• I understand that DRC-clean is necessary but not sufficient.