Signal Integrity and EMC Fundamentals

• Energy travels in the dielectric, not in the copperThe signal is an electromagnetic field between the trace and its reference plane; the copper merely guides it. Once you internalise this, return paths, plane splits, layer changes and connector transitions all stop being rules to memorise and become obvious consequences.
• Return current follows the path of least impedanceAt DC that means the path of least resistance, which spreads across the whole plane. Above about 100 kHz it means the path of least inductance, which is directly beneath the signal trace. This is why the plane beneath a fast trace matters and why a split under it forces a detour that radiates.Above ~100 kHz, return current concentrates within a few trace-heights of the signal's footprint on the reference plane.
• Edge rate, not clock rate, determines bandwidthA 1 MHz clock with 1 ns edges contains significant energy up to hundreds of megahertz. The knee frequency rule gives you the bandwidth you must design for. Slowing edges deliberately — with series resistors or with a driver's slew-rate control — is one of the cheapest EMC fixes available.f_knee ~ 0.5 / t_rise. A 1 ns edge has content to ~500 MHz.
• When a trace becomes a transmission lineIf the signal's round-trip propagation time exceeds the edge rise time, reflections matter and the trace must be treated as a transmission line with matched impedance and termination. Below that, it is a lumped connection and you can ignore impedance.Critical length ~ t_rise / (2 x propagation delay per unit length). For a 1 ns edge on microstrip: about 80 mm.
• Termination optionsSeries (source) termination places a resistor at the driver to match its output impedance to the line, and works well for point-to-point CMOS. Parallel termination at the receiver dissipates DC power but suits multi-drop. AC termination adds a capacitor to remove the DC loss. Choose from topology and power budget.
• CrosstalkAdjacent traces couple capacitively and inductively. Coupling falls off rapidly with separation relative to the height above the reference plane. The standard guidance of keeping spacing at three times the dielectric height is a consequence, not a magic number. Guard traces help only if they are stitched to ground frequently; unstitched, they make things worse.The 3W rule: spacing >= 3x the dielectric height reduces crosstalk to a few percent.
• Radiated emissions: the three mechanismsDifferential-mode radiation from current loops on the board, common-mode radiation from cables driven by ground-noise voltages, and direct radiation from apertures and slots in shielding. In practice cables dominate: a board with a perfect layout and a noisy ground reference at a connector will still fail.
• Designing for the pre-compliance testThe cheapest EMC strategy is to design in the standard mitigations from the start — solid planes, short return paths, series resistors on clocks, common-mode chokes and filtering on every cable, ESD protection at connectors, and a deliberate chassis-ground strategy — because retrofitting them costs a board spin.

ProblemA 25 MHz SPI clock with 1.5 ns edges runs 60 mm from an MCU to a flash chip on a 4-layer board. Does it need series termination?

1. 1
   Compute the knee frequency: f_knee = 0.5 / 1.5e-9 = 333 MHz. This is the bandwidth you must design for — far above the 25 MHz clock rate. This is the number that surprises people.
2. 2
   Compute the critical length: propagation delay on microstrip is about 6 ps/mm. Round-trip time for 60 mm = 2 x 60 x 6 ps = 720 ps.
3. 3
   Compare to the edge rate: 720 ps versus a 1.5 ns rise time. The round trip is about half the rise time. The conventional threshold is that termination matters when the round trip exceeds roughly one third to one half of the rise time, so this is right at the boundary.
4. 4
   At the boundary, expect visible overshoot and ringing but probably functional operation. The risks are: overshoot above the receiver's absolute maximum input voltage (which is a reliability problem, not just a cosmetic one), false clocking on the ringing if it crosses the threshold, and radiated emissions at the ringing frequency.
5. 5
   Estimate the ringing frequency: it is set by the round trip, so roughly 1/(2 x 720 ps) = 694 MHz. That is squarely in the range measured by radiated emissions testing.
6. 6
   Design the series termination anyway, because it costs one resistor. The MCU's output impedance is typically 20-50 ohm (check the datasheet, or the drive-strength setting). The trace impedance from your stackup is, say, 50 ohm. Series resistor R = Z0 - Z_driver = 50 - 30 = 20 ohm. Use 22 ohm (E24).
7. 7
   Place it at the driver, within a few millimetres of the MCU pin. Placed at the receiver end it does nothing for reflections; this is a common and completely ineffective mistake.
8. 8
   Check the effect on timing: the series resistor with the receiver's input capacitance (say 5 pF) plus the trace capacitance (about 60 mm x 1 pF/cm = 6 pF) forms an RC of 22 x 11e-12 = 242 ps. That adds to the rise time at the receiver. Against a 20 ns clock period this is negligible; against a 2 ns period it would not be.
9. 9
   Now consider the alternative: reduce the driver's slew rate if the MCU offers a drive-strength setting. Slowing the edge to 4 ns raises the critical length to about 330 mm, removing the transmission line problem entirely and reducing the knee frequency to 125 MHz. This is free, it is a firmware setting, and it is the single most effective EMC measure available on most microcontrollers.
10. 10
    Verify at bring-up: probe the clock at the receiver with a short-ground scope probe, measure overshoot against the receiver's absolute maximum, and measure the actual rise time. Adjust the resistor if needed — this is why a 0603 resistor rather than a zero-ohm link is worth fitting.

AnswerRight at the threshold, so fit a 22 ohm series resistor at the driver. But the better answer is to reduce the driver's slew rate in firmware, which raises the critical length beyond the trace length, cuts the knee frequency by 2.7x, and costs nothing. Always check for a drive-strength setting before adding components.

Tool: ngspice transmission line simulation plus scope verification

• Model the trace as a lossless transmission line. Create reflect.cir:

  Unterminated trace
  Vdrv src 0 PULSE(0 3.3 0 1.5n 1.5n 20n 40n)
  Rdrv src d 30
  T1 d 0 rx 0 Z0=50 TD=360p
  Crx rx 0 5p
  .tran 10p 60n
  .end

• TD = 360 ps is the one-way delay for 60 mm at 6 ps/mm.
• Run and: plot v(d) v(rx). You should see overshoot and ringing at the receiver, with the step arriving 360 ps late.
• Measure the overshoot: meas tran vmax MAX v(rx). Compare it to a typical 3.6 V absolute maximum input rating.
• Add series termination: change Rdrv from 30 to 52 (30 ohm driver plus a 22 ohm resistor). Re-run and plot again. The overshoot should largely disappear and the waveform should show a clean single step.
• Note the trade: with series termination the receiver initially sees only half the voltage until the reflection returns, which is why series termination only works for point-to-point, not multi-drop.
• Try parallel termination instead: remove the series resistor, add 'Rterm rx 0 50'. Observe a clean waveform but compute the DC current: 3.3/50 = 66 mA continuously while high. That is 220 mW for one signal — usually unacceptable.
• Now slow the edge: change the PULSE rise and fall times from 1.5n to 4n with no termination. Observe the ringing largely disappear because the round trip is now small relative to the edge.
• Verify on real hardware: probe a real SPI or clock line with a 10x probe and a ground spring (not the crocodile lead — see the oscilloscope skill). Measure overshoot, undershoot and ringing frequency. Compare to your simulation.
• If you have a near-field probe (or can make one from a small loop of coax), sweep it over the board while the bus runs and find the hot spots. This is a genuinely useful, nearly free pre-compliance technique.

• Rick Hartley - How to Achieve Proper Groundingfreevideo~90 minFree and the best single introduction to return current, plane splits and where the energy actually is. Essential for this skill.
• Signal Integrity Academy (Eric Bogatin, hosted by Teledyne LeCroy)freevideo~180 minFree video lecture library, registration required. Look for the material on when a trace becomes a transmission line, on termination, and on the knee frequency.
• Henry Ott - EMC resources and application notesfreereference~90 minFree technical tips from one of the field's authorities. The material on grounding, cable shielding and PCB layout for EMC is directly applicable.
• Your MCU's GPIO drive strength and slew rate registers (RP2040 shown)freedatasheet~30 minFind the drive-strength and slew-rate control registers in your own microcontroller's reference manual — in the RP2040 datasheet they are in the GPIO pad control section. This is the cheapest EMC control you have and most designers never touch it.

Perform a signal integrity and EMC review of your routed board, quantify the risks, implement the mitigations, and produce a pre-compliance plan.

Deliverables

• A signal inventory: every net with an edge rate faster than 10 ns, its measured or estimated rise time, its knee frequency, its routed length, and its critical length, with a verdict on whether it needs transmission-line treatment.
• A termination decision for every net that needs it, with the driver output impedance from the datasheet, the trace impedance from the stackup, the resistor value, and its placement.
• A return path audit: for every signal above the knee-frequency threshold, the reference plane it uses, every layer transition, the stitching via distance, and confirmation that no plane split is crossed. Screenshots evidencing each.
• A crosstalk analysis for the three most sensitive victim nets: the aggressors, the parallel run length, the separation relative to dielectric height, and the resulting coupling estimate against the 3W guidance.
• An ngspice reflection simulation for the worst-case net, unterminated and terminated, with the overshoot measured in both cases and compared against the receiver's absolute maximum input voltage.
• A slew-rate control plan: which drivers have configurable drive strength, what setting you will use, and the resulting knee frequency reduction.
• A cable and connector EMC plan: every cable leaving the board, its filtering (common-mode choke, ferrite, capacitors), its ESD protection, and the ground strategy at the connector.
• A pre-compliance test plan: what you will measure, with what equipment (including a home-made near-field probe if that is what you have), what a pass looks like, and what your first three mitigations would be if it fails.
• If you have hardware: near-field probe measurements over the board with the hot spots identified and photographed.

Acceptance criteria — how you know it is good enough

• Knee frequency is computed from edge rate for every fast net, not assumed from clock rate.
• Critical length is computed and compared against routed length for every fast net.
• Series terminations are placed at the driver, and this is verified in the layout.
• No fast signal crosses a plane split, and every layer transition has a stated stitching via distance.
• The reflection simulation shows a measured overshoot compared against a real absolute maximum rating.
• Slew-rate control is investigated and used where available.
• Every cable leaving the board has a filtering and ESD plan.

If you want to push further

• Build a near-field probe from semi-rigid coax and use it with a spectrum analyser or an SDR to find your board's dominant emission frequency, then correlate it to a specific signal.
• Model a plane split under a fast trace in a field solver (or with the ngspice transmission line model plus an added inductance) and quantify the impedance discontinuity it creates.

• I compute knee frequency from edge rate and design for that bandwidth.
• I know when a trace becomes a transmission line and can compute the critical length.
• I place series terminations at the driver and can explain why the receiver end does nothing.
• I trace return currents and never let a fast signal cross a plane split.
• I use slew-rate control as a first-line EMC measure.
• I plan filtering and ESD protection for every cable leaving the board.
• I can produce a pre-compliance plan with the equipment I actually have.