Decoupling and Power Integrity

• Decoupling is an impedance problemA chip drawing a fast current transient will see a voltage droop equal to that current times the impedance of the power delivery network at the relevant frequency. The design goal is therefore to keep the PDN impedance below a target across the frequency range that matters, not to 'add capacitors'.Z_target = allowed ripple voltage / transient current. For 3.3 V +/- 3% and a 1 A step: Z_target = 0.099 / 1 = 99 milliohm.
• Every capacitor is a series RLCBelow self-resonance it is a capacitor; above it, an inductor. The minimum impedance occurs at resonance and equals the ESR. This is why a single large capacitor cannot cover a wide frequency range, and why the answer involves several values.f_SRF = 1 / (2 x pi x sqrt(L_total x C)). Mounting inductance usually exceeds the capacitor's own ESL.
• Mounting inductance dominatesThe loop from the capacitor's pads, through the vias, to the planes and back typically contributes 1-2 nH, several times the capacitor's own ESL. This is why placement and via strategy matter far more than the capacitor's package specification, and why 'closer to the pin' is really 'smaller loop area'.
• The multiple-value folklore, examinedThe traditional advice of 100 nF plus 10 nF plus 1 nF in parallel creates anti-resonances between the capacitors, which can produce impedance peaks worse than the individual capacitors. Modern practice favours many capacitors of the same or a few values with low mounting inductance, sized so their combined resonance covers the band. Understand the anti-resonance mechanism before following either rule.
• The plane pair as a capacitorClosely spaced power and ground planes form a low-inductance capacitor that works at frequencies where discrete capacitors have already become inductive. Thin dielectric between the pair (say 0.1 mm rather than 0.5 mm) improves both the capacitance and the plane's spreading inductance substantially, and costs nothing but a stackup decision.
• Bulk, ceramic and the regulator's own bandwidthThe regulator handles DC to a few tens of kilohertz. Bulk capacitors (tens to hundreds of microfarads) cover from there to a few hundred kilohertz. Ceramics cover up to tens of megahertz. On-die and package capacitance covers above that. Design each band deliberately and know where the handoffs are.
• Return paths are part of the PDNA signal's return current flows in the reference plane directly beneath it. If that plane is split, or if the signal changes reference layers without a nearby stitching via, the return must detour, creating a large loop that both radiates and injects noise into the PDN. Power integrity and signal integrity are the same problem viewed from different ends.
• How much is enoughYou can compute a target impedance from the allowed droop and the transient current, then select capacitors to meet it. For most digital boards a simpler heuristic works: one 100 nF per supply pin placed as close as possible, plus 1-10 uF bulk per rail per device, plus a good plane pair. Use the heuristic and know how to do the real calculation when it matters.

ProblemA microcontroller on a 3.3 V rail draws up to 120 mA, with a worst-case transient step of 80 mA when its radio turns on, with an edge rate implying content up to 20 MHz. The rail must stay within +/-3%. Is 4 x 100 nF plus 1 x 10 uF sufficient?

1. 1
   Target impedance: allowed droop = 3.3 x 0.03 = 99 mV. Z_target = 0.099 / 0.080 = 1.24 ohm. This is a relatively relaxed target; high-current FPGA rails have targets in single-digit milliohms.
2. 2
   Frequency range of interest: from the regulator's loop bandwidth (say 50 kHz) up to 20 MHz.
3. 3
   The 10 uF bulk: assume a 0805 X5R rated 16 V, derated at 3.3 V to about 7 uF effective. Its impedance at 50 kHz is 1/(2 x pi x 50e3 x 7e-6) = 0.45 ohm. Below target. Good.
4. 4
   Its self-resonant frequency with 1.5 nH of mounting inductance: f = 1/(2 x pi x sqrt(1.5e-9 x 7e-6)) = 1.55 MHz. Above that it is inductive.
5. 5
   At 20 MHz the 10 uF behaves as 1.5 nH: Z = 2 x pi x 20e6 x 1.5e-9 = 0.19 ohm. Still below the 1.24 ohm target, because the target is generous.
6. 6
   The 100 nF capacitors: each with 1.5 nH mounting inductance resonates at 1/(2 x pi x sqrt(1.5e-9 x 100e-9)) = 13 MHz. Four in parallel gives an effective 0.375 nH, so Z at 20 MHz = 2 x pi x 20e6 x 0.375e-9 = 0.047 ohm.
7. 7
   Combined at 20 MHz: roughly 0.047 ohm in parallel with 0.19 ohm = 0.038 ohm. Far below the 1.24 ohm target.
8. 8
   Check the anti-resonance between the 10 uF and the 100 nF group. It occurs where the 10 uF is inductive and the 100 nF group is still capacitive, roughly between 1.5 and 13 MHz. The peak impedance there is set by the ESRs. With ceramic ESRs of 5-20 milliohm the peak is small; with an electrolytic bulk capacitor of 500 milliohm ESR it would be damped rather than peaked. Either way, well under target here.
9. 9
   Verdict: comfortably sufficient. The design passes with more than an order of magnitude of margin, which is normal for a small microcontroller.
10. 10
    Now change the problem: an FPGA core rail at 1.0 V +/- 3% with a 5 A transient. Z_target = 0.03/5 = 6 milliohm. Now the mounting inductance of every capacitor matters enormously, you need many capacitors in parallel, and the plane pair and its dielectric thickness become design parameters rather than defaults. The method is identical; only the numbers make it hard.
11. 11
    Lesson: compute the target first. It tells you whether this is a five-minute job or a week's work.

AnswerYes, with large margin — the combined PDN impedance is about 38 milliohm at 20 MHz against a 1.24 ohm target. But the value of the exercise is the method: computing Z_target first tells you immediately whether the standard heuristic suffices or whether you have a real power integrity problem.

Tool: KiCad stackup, zones and via stitching, plus a spreadsheet PDN impedance model

• Build a spreadsheet with a frequency axis from 1 kHz to 100 MHz (logarithmic, about 10 points per decade).
• For each capacitor type, model Z(f) = sqrt(ESR^2 + (2*pi*f*L_mount - 1/(2*pi*f*C_eff))^2). Use C_eff after DC bias derating, and L_mount of 1.5 nH unless you have a better figure.
• Plot each capacitor's impedance and the parallel combination of all of them. Add a horizontal line at your computed Z_target.
• Identify the frequency at which the combination first exceeds the target, if any. That is where you need more or different capacitors.
• Experiment: replace four 100 nF with eight 47 nF and observe the change. Replace the 0805 bulk with two 0603 parts and observe the effect of lower mounting inductance.
• Now in KiCad: open Board Setup > Physical Stackup. Configure a 4-layer board and set the dielectric thicknesses. Place the power and ground planes adjacent with a thin dielectric between them (e.g. signal / GND / PWR / signal with 0.2 mm between the planes).
• Compute the plane pair capacitance: C = e0 x er x A / d. For 100 mm x 80 mm of overlapping plane with 0.2 mm of FR-4 (er = 4.3): C = 8.85e-12 x 4.3 x 0.008 / 0.0002 = 1.5 nF. Small, but with essentially zero inductance it dominates above 100 MHz.
• Place decoupling capacitors on the same side as the IC where possible, with their vias placed to minimise the loop: vias immediately adjacent to the pads, not at the end of a trace stub.
• Add ground stitching vias around the board and especially near any layer transition of a fast signal. Use KiCad's via stitching or place them manually.
• Use the 3D viewer and layer visibility to check that no plane split runs under a fast signal.
• Finally, run DRC and check the zone fills actually connect the way you expect — an unfilled or islanded zone is a common and invisible layout error.

• Rick Hartley - How to Achieve Proper Groundingfreevideo~90 minFree conference talk. The clearest available explanation of return current, plane pairs and why the field, not the copper, carries the energy. Watch it twice.
• Signal Integrity Academy (Eric Bogatin, hosted by Teledyne LeCroy)freevideo~180 minFree video lecture library, registration required. Rigorous and quantitative. The material on PDN target impedance and on capacitor mounting inductance is directly applicable to this skill.
• Murata / TDK capacitor S-parameter and impedance datafreeinteractive~45 minFree tool giving real measured impedance versus frequency for specific part numbers, including ESR and ESL. Use it to replace your spreadsheet's assumptions with real data.
• KiCad board setup and stackup documentationopen licencedoc~45 minRead the physical stackup, zones and net classes sections. You will configure a real stackup in the layout skills.

Design and justify the complete power delivery network for a mixed-signal board with a microcontroller, a switching regulator, an ADC and a radio, on a 4-layer stackup.

Deliverables

• A target impedance calculation for each rail: allowed droop from the device's specification, the transient current with its source (datasheet or estimate with reasoning), the resulting Z_target, and the frequency range of interest with its upper limit justified by edge rate.
• A PDN impedance model in a spreadsheet for the most demanding rail, plotting each capacitor and the combination against the target, with real capacitor data (ESR, ESL, derated C) from a manufacturer tool.
• An anti-resonance analysis: identify any impedance peak in the combined plot, state its frequency and magnitude, and either show it is below target or state the change that fixes it.
• A capacitor placement plan: for each supply pin, the assigned capacitor, its package, and its distance and via arrangement, with the mounting loop described.
• A stackup design: four layers with the assignment of each, the dielectric thicknesses, the plane pair separation, and the resulting plane capacitance computed.
• A return path analysis: identify every fast signal that changes reference layers, and show the stitching via that provides its return path. Identify every plane split and show that no fast signal crosses it.
• A KiCad board implementing the placement and stackup for at least the microcontroller and regulator sections, with screenshots evidencing each of the above.
• A written critique of the '100 nF plus 10 nF plus 1 nF' folklore using your own impedance plot as evidence.

Acceptance criteria — how you know it is good enough

• Z_target is computed from a real droop allowance and a justified transient current, not assumed.
• The impedance model uses real manufacturer data including derating, not idealised capacitors.
• Anti-resonance is explicitly examined, not ignored.
• Every supply pin has an assigned capacitor with a described mounting arrangement.
• The stackup places power and ground planes adjacent, and the plane capacitance is computed.
• No fast signal crosses a plane split, and every layer transition has a nearby stitching via.

If you want to push further

• Measure a real board's PDN impedance with a two-port VNA measurement (or a signal generator and scope approximation) and compare to your model.
• Model the effect of removing the plane pair (moving to a 2-layer board) and quantify the impedance degradation above 10 MHz.

• I compute a PDN target impedance before selecting decoupling capacitors.
• I model capacitors as series RLC with real mounting inductance, not as ideal capacitors.
• I account for DC bias derating in PDN calculations.
• I can explain anti-resonance and check for it.
• I place power and ground planes adjacent and know why the dielectric thickness matters.
• I trace return currents and never let a fast signal cross a plane split.
• I can defend or refute decoupling folklore with an impedance plot.