Switching Regulators and Their Layout

• How a buck worksA switch connects the inductor to the input for a fraction D of each cycle, then a diode or synchronous FET connects it to ground. The inductor averages the chopped voltage. Output voltage is the input times the duty cycle, and the control loop adjusts D to hold the output constant.Vout = D x Vin for a buck in continuous conduction mode.
• Ripple current sets the inductorThe inductor current ramps up during the on-time and down during the off-time. The peak-to-peak ripple is set by the inductance, the voltage across it and the on-time. Design convention is 20-40% of maximum load current: less ripple needs a bigger inductor, more ripple needs bigger capacitors and raises peak current.dI = Vout x (1 - D) / (L x f_sw). Choose L for dI = 0.3 x Iout(max). Peak current = Iout + dI/2.
• Output capacitor and output rippleOutput voltage ripple has two components: the capacitance term (charge in and out over a cycle) and the ESR term (ripple current through the ESR). With ceramics the ESR term is often negligible; with electrolytics it dominates. Transient response — the dip when the load steps — is usually the binding requirement rather than steady-state ripple.V_ripple ~ dI / (8 x f_sw x C) + dI x ESR. Transient dip ~ dI_load x ESR + dI_load x t_response / C.
• CCM and DCMIn continuous conduction mode the inductor current never reaches zero. At light load it can, entering discontinuous conduction, where the transfer function and the loop dynamics change. Many converters deliberately enter a pulse-skipping or burst mode at light load for efficiency, at the cost of higher output ripple and audible noise if it lands in the audio band.
• The hot loop is the whole layout problemThe loop carrying the high-di/dt current — input capacitor, high-side switch, low-side switch or diode, and back — must have minimum area. Its inductance times di/dt is the voltage spike on the switch node, which is your ringing, your EMI and your device stress. Everything else in the layout matters less than this.Place the input capacitor's ground and the low-side return within a few millimetres, on the same layer, with no via detour. Minimise loop area first, then everything else.
• Feedback network and compensationA divider sets the output voltage from the reference. The loop's crossover frequency and phase margin determine transient response and stability. Internally compensated parts do this for you but constrain your output capacitance choice; externally compensated parts give control at the cost of needing to design a Type II or Type III network.
• Feedback routing and noiseThe feedback node is high impedance and low amplitude, sitting right next to a node that swings the full input voltage at megahertz. Route it away from the switch node, keep it short, and take the sense point at the load, not at the inductor. A noisy feedback node causes jitter, subharmonic oscillation, and output error.
• Input capacitance and the source impedanceThe input capacitor supplies the pulsed current the converter draws, so its RMS ripple current rating matters. It also interacts with the inductance of the supply wiring: a long input cable plus a ceramic input capacitor forms a resonant tank that can ring dangerously on hot-plug. Damping this is a real design task, not a theoretical one.

ProblemDesign the power stage for a 12 V (9-15 V range) to 5 V, 2 A synchronous buck switching at 500 kHz. Target 30% ripple current and 50 mV output ripple.

1. 1
   Duty cycle: D = Vout/Vin. At nominal 12 V, D = 5/12 = 0.417. At 9 V, D = 0.556. At 15 V, D = 0.333.
2. 2
   Inductor ripple is worst at maximum input voltage (longest off-time). Use Vin = 15 V, D = 0.333.
3. 3
   Target ripple: dI = 0.30 x 2 A = 0.6 A.
4. 4
   Inductance: L = Vout x (1 - D) / (dI x f_sw) = 5 x (1 - 0.333) / (0.6 x 500e3) = 5 x 0.667 / 300000 = 11.1 uH.
5. 5
   Choose the nearest standard value: 10 uH. Recompute actual ripple: dI = 5 x 0.667 / (10e-6 x 500e3) = 0.667 A, which is 33% of 2 A. Acceptable.
6. 6
   Peak inductor current: I_peak = 2 + 0.667/2 = 2.33 A. The inductor's Isat must exceed this with margin — target Isat >= 3.5 A to cover transients and current limit.
7. 7
   Irms through the inductor is essentially the DC output current, 2 A, so the inductor's Irms rating must exceed 2 A with margin for its own heating.
8. 8
   Inductor DCR: choose a part with DCR around 20-30 milliohm. Conduction loss = 2^2 x 0.025 = 100 mW.
9. 9
   Output capacitor from ripple: the capacitance term gives V = dI/(8 x f x C), so C = 0.667/(8 x 500e3 x 0.050) = 3.3 uF. The ESR term with ceramics (say 3 milliohm) gives 0.667 x 0.003 = 2 mV, negligible.
10. 10
    But transient response usually dominates. For a 1 A load step with a loop bandwidth of 50 kHz, the dip is roughly dI_load/(2 x pi x f_bw x C). For a 100 mV dip: C = 1/(2 x pi x 50e3 x 0.1) = 32 uF.
11. 11
    Choose 2 x 22 uF 0805 X5R 16 V. Check DC bias derating at 5 V: an 0805 22 uF 16 V part may fall to about 12 uF each, so 24 uF effective. Close to the 32 uF target — add a third, or accept a slightly larger dip. Add a third: 3 x 22 uF nominal, ~36 uF effective.
12. 12
    Input capacitor RMS ripple current: I_rms = Iout x sqrt(D x (1 - D)). Worst at D = 0.5: 2 x 0.5 = 1.0 A RMS. Choose ceramics with combined ripple rating well above 1 A — typically 2 x 10 uF 25 V X7R plus a 100 nF, and check the parts' ripple ratings.
13. 13
    Feedback divider: if the reference is 0.8 V, the ratio is 5/0.8 = 6.25. With a bottom resistor of 10 k, the top is 52.5 k; use 52.3 k (E96) giving 5.03 V. Check the divider current is well above the feedback pin's bias current — 0.8/10k = 80 uA, versus a typical 50 nA bias. Fine.
14. 14
    Switching losses and thermals: for a synchronous part with 30 milliohm FETs, conduction loss ~ I^2 x Rds(on) x D for the high side plus the same for the low side over (1-D): 4 x 0.03 = 120 mW total. Switching loss depends on the transition time and dominates at high Vin. Estimate total losses at 400-600 mW and check the package's Rth.
15. 15
    Efficiency estimate: output power 10 W, losses ~0.7 W including the inductor, so about 93%. Compare to an LDO's 42% for the same conversion — 7 W of heat versus 0.7 W. That is why this converter exists.

Answer10 uH inductor with Isat >= 3.5 A and Irms >= 2.5 A, 3 x 22 uF ceramic output (36 uF effective after derating), 2 x 10 uF 25 V input with 1 A RMS ripple capability, 52.3 k / 10 k feedback divider. Peak inductor current 2.33 A, output ripple well under 50 mV, efficiency about 93%.

Tool: KiCad layout of a buck converter hot loop, plus a vendor design tool for cross-checking

• First, cross-check your maths. Most switching regulator vendors publish a free web-based design tool for their parts. Enter your Vin range, Vout, Iout and frequency and compare its recommended inductor and capacitors to your hand calculation. Where they differ, find out why — usually a different ripple assumption.
• In KiCad, place the regulator IC. Immediately place the input ceramic capacitors as close as physically possible to the VIN and GND pins, on the same layer, with no vias between them and the IC.
• Draw the hot loop with the measurement tool: from the input capacitor's positive terminal, through the IC's VIN pin, through the internal switches, out of the GND pin, back to the input capacitor's ground terminal. Measure this loop's enclosed area. Your goal is to make it as small as the parts allow.
• Place the inductor next, close to the switch node pin. Keep the switch node copper small — it is the noisiest net on the board and copper area is antenna area. This is the one place where wider is worse.
• Place the output capacitors after the inductor, with their ground returning to the same ground region as the input capacitors.
• Route the feedback trace last, as a thin trace, on a layer away from the switch node, taking its sense point at the output capacitors (or at the load if remote sensing). Never route it under the inductor.
• Add a ground plane on the layer directly beneath the power stage, unbroken under the hot loop. The image current in that plane is what actually cancels the loop inductance.
• Use KiCad's 3D viewer and the layer visibility controls to check that no signal trace crosses under the switch node.
• Run DRC with a rule set that includes adequate clearance for the input voltage.
• Finally, compute the trace width for the 2 A output path using the PCB Calculator's Track Width tab, and verify your routed widths meet it.

• TI - Basic Calculation of a Buck Converter's Power Stage (SLVA477)freereference~60 minFree PDF, eight pages, and it contains every equation in the worked example. The single most useful document for this skill.
• TI SNVA803 - Improve DC/DC Regulator EMI Performance With Optimized Power Stage Layoutfreereference~60 minFree PDF, and the clearest treatment of the hot loop there is: why its area sets your EMI, and how to place the input capacitors and the ground return. Read alongside your chosen part's datasheet layout section.
• Robert Feranec - power supply layout videosfreevideo~120 minSearch for switching regulator layout. Watching an experienced engineer place a hot loop and explain each decision is worth several readings.
• Your chosen regulator's datasheet layout section and evaluation module documentationfreedatasheet~60 minVendors publish full gerbers and layouts for their evaluation modules. Download one and study the placement — it is a free, expert-designed reference layout.

Design a complete synchronous buck converter — schematic, component selection with full calculations, and a laid-out power stage — for a specification you set (for example 12 V nominal to 3.3 V at 3 A), and defend the layout against a written checklist.

Deliverables

• A specification: input range, output voltage and tolerance, maximum and minimum load, switching frequency, target efficiency, maximum output ripple, and the transient response requirement (load step size and allowed dip).
• A full power stage calculation: duty cycle across the input range, inductor value from ripple current at worst-case input, peak and RMS inductor current, chosen inductor part with Isat, Irms and DCR quoted, output capacitance from both ripple and transient requirements including DC bias derating, and input capacitance with its RMS ripple current requirement.
• A loss budget: inductor DCR loss, switch conduction loss, switching loss estimate, and the resulting efficiency and junction temperature for the regulator IC.
• A feedback network design with real E96 values, the resulting output voltage, and a check that the divider current is far above the feedback pin bias current.
• A cross-check against the vendor's own design tool, with a table of your values next to its values and an explanation of every difference greater than 20%.
• A KiCad layout of the power stage on at least two layers, with the hot loop area measured and stated in square millimetres, the switch node area minimised, the feedback trace routed away from the switch node, and a solid ground reference beneath.
• A layout self-review against a written checklist of at least ten items drawn from the vendor's layout guidelines, with each item marked pass and evidenced by a screenshot or a measurement.
• A statement of what you would measure on the first prototype to verify the design, and what a bad result would look like.

Acceptance criteria — how you know it is good enough

• The inductor is chosen against peak current at worst-case input, and Isat exceeds it with stated margin.
• Output capacitance is checked against both ripple and transient requirements, using derated effective capacitance.
• Input capacitor RMS ripple current is computed and the chosen parts are rated for it.
• The hot loop area is measured and stated, and the input capacitors have no vias between them and the IC.
• The feedback trace does not run under or adjacent to the switch node, and the sense point is at the output capacitors or the load.
• The layout checklist has at least ten items, each evidenced rather than asserted.

If you want to push further

• Design the compensation network for an externally compensated controller: compute the crossover frequency and phase margin, and show the Bode plot from a simulation.
• Add input hot-plug damping (an electrolytic or a series RC across the ceramic input capacitance) and calculate the resonance you are damping.

• I can size a buck inductor from ripple current and check it against Isat and Irms.
• I size output capacitance from the transient requirement, not just the ripple requirement.
• I account for ceramic DC bias derating in every capacitor calculation.
• I compute input capacitor RMS ripple current and specify parts rated for it.
• I can identify the hot loop in any switching converter and minimise its area.
• I route feedback away from the switch node and sense at the load.
• I cross-check my design against a vendor tool and can explain every disagreement.