Linear Regulators and Thermal Design

• A linear regulator burns the differenceIt behaves as a controlled resistor between input and output. Efficiency is simply Vout/Vin, independent of how good the part is. Dropping 12 V to 3.3 V at 500 mA means 4.35 W of heat to save 1.65 W of useful power — 27% efficient. This single fact decides linear versus switching more often than anything else.P_dissipated = (Vin - Vout) x Iout + Vin x Iq. Efficiency = Vout / Vin.
• Dropout voltage and headroomThe minimum input-to-output difference for regulation to hold. A classic 7805 needs about 2 V; a modern LDO may need 100-300 mV at full load. Dropout is worst at high current and at low temperature, and a design that only checks the room-temperature typical figure will fail on a cold start.
• Stability and the output capacitorThe regulator's control loop is compensated assuming a particular output capacitance and ESR. Older LDOs need a minimum ESR and oscillate with ceramics; modern ceramic-stable parts need a minimum capacitance. Ceramic derating under DC bias can take you below that minimum without you noticing. This is a leading cause of mysterious oscillation.
• PSRR and noisePower supply rejection ratio describes how much input ripple is attenuated, and it falls off with frequency — an LDO with 70 dB at 1 kHz may have 20 dB at 1 MHz, which is exactly where a switching regulator's ripple lives. Output noise (in microvolts RMS over a band) is a separate spec and matters for analogue and RF supplies.
• Quiescent current and ground currentFor battery products the regulator's own consumption when the load is idle can dominate the energy budget. Note that some parts' quiescent current rises sharply near dropout. Compare candidates on Iq at your actual load, not at no load.
• The thermal pathHeat flows from junction to case to board to air. Rth(j-a) from a datasheet assumes a specific test board; your board's copper area, layer count and via count change the number substantially. Thermal vias under a power pad connecting to an internal plane are the standard way to improve it.Tj = Ta + P x Rth(j-a). Design for Tj below 100-110 C even if Tj(max) is 125-150 C.
• Thermal shutdown and current limit are protections, not featuresA part that regulates by cycling in and out of thermal shutdown is not working; it is surviving. Similarly, current limit protects the part, not the load. If your design relies on either during normal operation, the design is wrong.

ProblemA 5 V to 3.3 V LDO supplies 400 mA in a sealed enclosure whose internal ambient reaches 55 C. The part is in an SOT-223 with a datasheet Rth(j-a) of 62 C/W on a 1 square inch copper pour, and Rth(j-c) of 15 C/W. Tj(max) is 125 C.

1. 1
   Dissipation: P = (5.0 - 3.3) x 0.4 = 0.68 W. Add quiescent: 5.0 x 0.003 = 15 mW. Total 0.695 W. Use 0.70 W.
2. 2
   But check worst-case input: at +5% the input is 5.25 V, so P = (5.25 - 3.3) x 0.4 + 0.016 = 0.796 W. Use the worst case: 0.80 W.
3. 3
   With the datasheet's 62 C/W: rise = 0.80 x 62 = 49.6 C. Tj = 55 + 49.6 = 104.6 C.
4. 4
   That is below 125 C, but only 20 C of margin, and it assumes your board has the full 1 square inch of copper the datasheet assumed. If your pour is 0.25 square inch, Rth might be 110 C/W, giving a rise of 88 C and Tj = 143 C — over the limit.
5. 5
   So the copper area is not a detail; it is the design. Check the datasheet's Rth versus copper area graph, which most power parts include, and read off the area needed for your target.
6. 6
   Target: keep Tj at or below 100 C. Allowed rise = 100 - 55 = 45 C. Required Rth(j-a) = 45 / 0.80 = 56 C/W. From a typical curve, that needs roughly 1.5 square inches of 1 oz copper on the same layer as the tab, or less if you add thermal vias to an internal plane.
7. 7
   Now question the architecture. 0.8 W of heat inside a sealed enclosure also raises the internal ambient itself — the 55 C figure may already be a consequence of this dissipation, or it may rise further.
8. 8
   Compare to a buck converter: at 90% efficiency, dissipation would be (3.3 x 0.4) / 0.9 x 0.1 = 0.15 W, five times less. The buck costs more parts, more board area, more noise and a harder layout, but removes the thermal problem entirely.
9. 9
   Decision: at 400 mA from 5 V, the LDO is defensible with adequate copper, and simpler. At 800 mA or from 12 V, it stops being defensible. Set that boundary explicitly in your design rules: linear regulators above roughly 1 W of dissipation deserve a second look.

AnswerTj = 105 C with the datasheet's assumed copper — acceptable but thin. Design to 1.5 square inches of pour plus thermal vias for Tj = 100 C. Above about 1 W of dissipation, switch to a buck converter instead.

Tool: KiCad PCB Calculator, thermal pour, and ngspice for the loop

• Draw the LDO circuit in KiCad: input bulk capacitor, input 100 nF, the regulator, output capacitor per the datasheet, output 100 nF, and the enable pull-up.
• Assign a footprint with an exposed pad or tab (SOT-223, DPAK, or a QFN with a thermal pad).
• In the PCB editor, place the regulator and draw a copper zone on the same layer as the tab, connected to the tab net. Use the zone properties to set it as a solid fill (not hatched) for thermal performance.
• Measure the pour area: KiCad shows zone area in the properties, or use the measurement tool to estimate. Compare to your required area from the thermal calculation.
• Add thermal vias: place a grid of vias inside the pad area connecting to an inner or bottom-layer copper pour on the same net. Use the datasheet's recommended via count and size if it gives one; otherwise 4-9 vias of 0.3 mm drill.
• Note KiCad's pad connection setting: by default zone connections to pads use thermal reliefs, which is exactly what you do NOT want on a thermal pad. Set the pad's zone connection to 'Solid' for the power tab.
• Verify with the 3D viewer that the pour is where you think it is.
• Now the stability check. In ngspice, model the output network: the specified minimum capacitance versus the actual capacitance after DC bias derating. Look up a real 10 uF 0805 X5R at your output voltage and find its effective capacitance — it may be 4 uF.
• Compare that derated value to the datasheet's minimum output capacitance for stability. If it is below, the design is unstable in production even though the BOM says 10 uF. Increase the value or the case size and recheck.

• TI - LDO basics series (free application notes)freereference~90 minThe LDO Basics series covers dropout, PSRR, noise, stability and thermals in short readable notes. Free PDFs.
• TI SLVA462 - Understanding Thermal Dissipation and Design of a Heatsinkfreereference~45 minUnderstanding thermal resistance parameters and why the datasheet number depends on the test board. Essential context for any power part.
• KiCad PCB editor manual - copper zones and thermal reliefsopen licencedoc~30 minRead the zone and pad connection sections. The thermal relief default is a trap for power pads.
• Three real LDO datasheets for the same voltage and currentfreedatasheet~60 minCompare dropout at full load and at -40 C, minimum Cout and ESR window, PSRR curve at 100 kHz, Iq at 100 mA, and the Rth vs copper area graph. The differences will surprise you.

Design and thermally verify the linear supply section of a board with three rails: 3.3 V digital at 250 mA from 5 V, 3.3 V analogue at 30 mA with low noise, and 1.8 V at 150 mA from 3.3 V. Enclosure ambient is 50 C.

Deliverables

• A regulator selection table for all three rails with real part numbers, comparing dropout at full load and at the low temperature extreme, minimum Cout with its ESR window, PSRR at 100 kHz, Iq at the actual load, and package thermal resistance.
• A full dissipation and junction temperature calculation for each rail at worst-case input voltage, maximum load and 50 C ambient, ending in a Tj figure with the margin to Tj(max) stated.
• A copper area requirement for each regulator derived from a datasheet Rth-versus-area curve, and a KiCad layout fragment showing pours of the calculated size with thermal vias.
• A capacitor stability check: the specified minimum output capacitance, the chosen part, its DC bias derating at the actual output voltage cited from a manufacturer curve, and the resulting effective capacitance compared to the minimum.
• A noise analysis for the analogue rail: the switching or digital ripple present on its input, the regulator's PSRR at that frequency, and the resulting ripple on the analogue rail in microvolts, compared against what your ADC's LSB is worth.
• An architecture decision note: for each rail, state whether a linear regulator is the right choice and at what load current you would switch to a buck, with the dissipation crossover computed.
• A power tree diagram with every rail, its source, current, dissipation and Tj.

Acceptance criteria — how you know it is good enough

• Dissipation is computed at worst-case input voltage, not nominal.
• Junction temperature is computed for every regulator with the copper area assumption stated explicitly.
• Output capacitor stability is checked against the derated effective capacitance, not the nameplate value.
• The analogue rail's noise is quantified in microvolts and compared to an ADC LSB.
• The linear-versus-switching crossover current is computed, not asserted.
• Every Tj has at least 20 C of margin to Tj(max).

If you want to push further

• Add a soft-start or inrush limit to the largest rail and calculate the peak input current without it.
• Measure a real LDO's PSRR by injecting a small sine on its input and measuring the output with a scope, and compare to the datasheet curve.

• I compute linear regulator dissipation at worst-case input and convert it to a junction temperature.
• I know that Rth(j-a) depends on my board's copper and I size the pour deliberately.
• I check dropout at full load and at the low temperature extreme.
• I verify output capacitor stability against the derated effective capacitance.
• I use PSRR at the actual ripple frequency, not the headline figure.
• I can state the dissipation at which a linear regulator stops being the right answer.