Serial Interfaces: UART, SPI and I2C

• UART: asynchronous, no clock, tolerance-limitedTwo devices agree a baud rate and each uses its own clock. The receiver resynchronises on the start bit and samples the middle of each subsequent bit. Accumulated clock error over a 10-bit frame must stay under half a bit, which is where the roughly 2% total budget comes from.Total baud error budget ~ +/-2% for 8N1 (split between both ends). A 1% error at each end is the practical limit.
• UART is not RS-232 and not RS-485UART describes the framing; RS-232 and RS-485 describe electrical layers. RS-232 uses +/-3 to +/-15 V inverted signalling and needs a transceiver. RS-485 is differential, multi-drop, needs termination and bias resistors, and requires direction control. Confusing the framing with the electrical layer is a common source of dead links.
• SPI: synchronous, full duplex, point-to-multipoint by chip selectOne clock, one data line each way, one chip select per peripheral. Fast and simple, but it costs a pin per device and it has no acknowledgement, no addressing and no error detection. The four modes (CPOL/CPHA) describe which clock edge launches and which captures; getting them wrong gives you shifted or inverted data.
• SPI topology trapsDaisy-chaining requires device support. A peripheral that does not tri-state MISO when deselected will corrupt the bus for everyone. Long SPI traces need series termination. And the chip select must be handled by hardware or with care, because a glitch on CS mid-transaction desynchronises the peripheral's bit counter.
• I2C: two wires, open-drain, addressed, acknowledgedMulti-drop on two wires with 7-bit addressing and per-byte acknowledgement. Every device is open-drain so any device can hold the clock low (clock stretching). The cost is speed, the pull-up power, the bus capacitance limit, and address collisions between devices from different vendors.Standard 100 kHz, Fast 400 kHz, Fast+ 1 MHz. Bus capacitance limit 400 pF for standard/fast mode.
• I2C failure modesA stuck bus (a peripheral holding SDA low because it was reset mid-transaction) needs a recovery sequence: clock out up to nine pulses until SDA releases, then issue a STOP. Address collisions require an address-select pin or a bus multiplexer. Slow rise times cause missed edges. Clock stretching beyond the master's timeout causes silent failures.
• Choosing between themPin count, speed, distance, number of devices, and whether you need acknowledgement. I2C for many slow sensors on few pins. SPI for high throughput to few devices. UART for a point-to-point link, especially off-board or to a host. The decision is usually made for you by the peripheral you must talk to.
• Debugging serial busesDecode first: a logic analyser with a protocol decoder tells you what was transmitted. Then look analogue: a scope tells you whether the edges are clean and the levels valid. The order matters — most failures are protocol or address errors, but the ones that are not are invisible to a logic analyser.

ProblemAn MCU with a +/-1.5% internal oscillator must talk 115200 baud 8N1 to a USB-serial bridge with a crystal (+/-0.05%). The MCU's baud generator divides a 48 MHz clock by an integer. Will it work?

1. 1
   Framing error budget: an 8N1 frame is 10 bit times (start, 8 data, stop). The receiver samples at the middle of each bit, so the sampling point must not drift more than half a bit by the last bit.
2. 2
   Drift at the last bit = 9.5 bit times x (total fractional error). Setting this less than 0.5 bit gives total error < 0.5/9.5 = 5.26%.
3. 3
   In practice receivers sample with a 16x oversampling clock and majority-vote three samples, which tightens the requirement. Use the conventional 2% total budget for a safe design, and 3% as an absolute limit.
4. 4
   Divider error: 48,000,000 / 115200 = 416.67. The integer divider gives 417, producing an actual baud of 48e6/417 = 115,107.9. Error = (115107.9 - 115200)/115200 = -0.08%.
5. 5
   If the part has a fractional divider, this term goes to nearly zero. Many modern parts do; check.
6. 6
   Oscillator error: +/-1.5% over temperature and voltage, from the datasheet's guaranteed column, not the trimmed-at-25 C typical.
7. 7
   Bridge error: +/-0.05% crystal, plus its own divider error, typically negligible.
8. 8
   Worst case total: 1.5% + 0.08% + 0.05% = 1.63%. Under the 2% budget.
9. 9
   But check the conditions on that 1.5%: many internal oscillators are specified at +/-1% over a narrow temperature range and +/-3% or worse over the full industrial range, or when running from a wide supply range. If your product sees -40 to +85 C, re-read the table.
10. 10
    Suppose the full-range figure is +/-3%. Total becomes 3.13%, over budget. The link will work at room temperature and fail in the field on cold mornings — the worst possible failure mode.
11. 11
    Options: (a) fit a crystal, (b) run at a lower baud rate (does not help — the error is fractional, not absolute), (c) use the USB or another timing reference to trim the internal oscillator at runtime, which several parts support, (d) accept a narrower operating temperature range and document it.
12. 12
    Note that (b) is a trap that catches people: baud rate error is a percentage, so slowing down does not improve it. Only reducing the frame length would, and 8N1 is already short.

AnswerIt works if the oscillator's guaranteed accuracy over your full operating temperature and voltage range is better than about 1.9%. Check the guaranteed full-range number, not the typical room-temperature one. If it is +/-3%, fit a crystal or trim the oscillator at runtime — lowering the baud rate does not help.

Tool: PulseView with I2C, SPI and UART decoders

• Set up a target with all three buses active. A microcontroller board with a sensor on I2C, a flash or display on SPI, and a USB-serial link is ideal.
• Capture UART first: connect one channel to TX and one to ground. Sample at least 10x the baud rate — for 115200 baud, use 2 MHz or more.
• Add the UART decoder and set the baud rate, data bits, parity and stop bits. If you do not know the baud rate, measure the narrowest pulse with cursors: baud = 1/narrowest_bit_time.
• Now break it deliberately: set the decoder to the wrong baud rate and observe the garbage. This is exactly what a real mismatched link looks like, and recognising the pattern saves hours.
• Capture SPI: four channels (SCK, MOSI, MISO, CS). Add the SPI decoder and set CPOL and CPHA. Cycle through all four mode combinations and observe how the decoded bytes change. Only one is correct — identify it and explain why from the waveform.
• Capture I2C: two channels plus ground. Add the I2C decoder. Read the address, the R/W bit and the ACK/NAK of each byte.
• Break I2C deliberately: disconnect the pull-up on SDA (or increase it substantially) and re-capture. Observe the slow rise and the resulting decode failures. Switch to a scope on the same signal to see the RC curve the logic analyser was hiding.
• Simulate a stuck bus: hold SDA low manually and observe that the master cannot issue a START. Then implement the recovery sequence — nine clock pulses followed by a STOP — and capture it working.
• Save all captures as .sr files with descriptive names. These are your project evidence.

• NXP UM10204 - I2C-bus specificationfreedoc~120 minThe definitive free specification. Read the protocol section, the electrical section and the bus recovery guidance.
• SparkFun tutorials: Serial Communication, I2C, SPIopen licencereading~90 minCC BY-SA. Clear introductions to all three buses with good diagrams. Read all three tutorials.
• sigrok protocol decoder list and documentationopen licencedoc~30 minSee what decoders exist, including device-specific ones that stack on top of the raw bus decoders.
• SparkFun - Serial Peripheral Interface (SPI)open licencereading~30 minCC BY-SA. The CPOL/CPHA mode table with waveforms, plus the chip-select and daisy-chain topologies. Print the mode table; you will refer to it every time you bring up a new SPI peripheral.

Design the serial interface layer for a multi-sensor board and prove it works with captured, decoded, timing-verified evidence, including a documented diagnosis of at least two injected faults.

Deliverables

• A bus allocation decision: given at least four peripherals with differing speed and pin-count requirements, assign each to I2C, SPI or UART with a written justification referencing throughput, pin cost, distance and addressing.
• An I2C bus design: address map for every device (with the actual 7-bit addresses from datasheets and any collision resolved), bus capacitance estimate, pull-up sizing worked from both constraints, and rise-time verification.
• A SPI design: mode (CPOL/CPHA) for each peripheral cited from its datasheet, the timing budget at your intended clock rate with setup and hold margins, chip-select handling, and series termination if needed.
• A UART budget: baud rate, framing, the accuracy requirement computed from frame length, and evidence from datasheets that both ends meet it over the full operating temperature range.
• Captured .sr files for all three buses, with annotated screenshots showing a correctly decoded transaction and an explanation of what the device was being asked to do.
• Two fault diagnoses: inject a fault (wrong SPI mode, missing or oversized I2C pull-up, baud mismatch, address collision, or a stuck I2C bus), capture it, describe the symptom as it would appear to a firmware engineer, show the capture that identifies the true cause, and show the fix verified by a second capture.
• An I2C bus recovery routine described at the signal level, with a capture of it working.
• A statement of what a logic analyser could not have told you, backed by at least one scope capture of an analogue problem.

Acceptance criteria — how you know it is good enough

• Every I2C address is taken from a real datasheet and collisions are explicitly checked.
• Pull-up sizing uses both the sink-current and rise-time constraints and the result is verified by measurement or simulation.
• SPI modes are cited from datasheets and the timing budget shows both setup and hold margins.
• The UART accuracy analysis uses guaranteed full-temperature-range oscillator specs.
• Both fault diagnoses include the symptom, the capture that identified the cause, and a verified fix.
• At least one problem is demonstrated to be invisible to a logic analyser and visible on a scope.

If you want to push further

• Add an RS-485 segment with correct termination, failsafe biasing and direction control, and capture a transaction including the turnaround.
• Write a custom sigrok decoder for one of your sensors that translates raw I2C into named register reads and writes.

• I can choose between UART, SPI and I2C from real requirements.
• I can compute a UART baud accuracy budget and check it against guaranteed oscillator specs.
• I can determine the correct SPI mode from a datasheet timing diagram.
• I can size I2C pull-ups and verify the rise time by measurement.
• I can capture and decode all three buses with open-source tools.
• I can diagnose a failing bus and distinguish protocol faults from electrical ones.
• I know the I2C bus recovery sequence and can demonstrate it.