Combinational Logic Design

• Combinational means memorylessThe output is a pure function of the present inputs. No feedback, no state. The moment you feed an output back into the network you have made a latch, sometimes by accident — this is the single most important boundary in digital design.
• The standard blocksDecoder (n inputs to 2^n one-hot outputs), encoder and priority encoder (the reverse), multiplexer (select one of many), demultiplexer, comparator, and adder. Nearly all combinational design is composition of these, not gate-level work.
• Multiplexers are universalA 2^n-to-1 mux with the inputs tied to constants implements any n-variable function directly from its truth table. This is why FPGA lookup tables exist and why 'implement it in a mux' is often the fastest path from a truth table to hardware.
• Propagation delay and the critical pathEvery gate has a delay from input change to output settling. The longest path through the network sets the maximum frequency at which the block can be used. Adding gate levels to save gate count trades speed for area — the fundamental combinational trade-off.Block delay = sum of gate delays along the longest path. This becomes t_pd in your timing budget.
• Ripple carry versus carry lookaheadA ripple carry adder's delay grows linearly with width because each stage waits for the previous carry. Carry lookahead computes carries in parallel, giving logarithmic delay at the cost of far more gates. This is the canonical example of the speed/area trade.
• Hazards and glitchesWhen two inputs change nearly simultaneously, a combinational output can momentarily take a wrong value even though the final value is correct. A static hazard can be removed by adding a redundant K-map term. This matters enormously when the output drives an asynchronous input like a clock, a reset or a chip select.Glitches are harmless into a synchronous flip-flop's D input. They are dangerous on clocks, resets, enables and write strobes.
• Fan-out and loadingEach driven input presents capacitance; more loads means slower edges and more delay. Real logic families specify fan-out limits. Exceed them and edges slow enough to cause false triggering and excess current in the receiving gate.
• Don't build what you can buy or inferFor discrete logic, a single 74HC-series part usually replaces a handful of gates. In an FPGA or CPLD, describing the function in HDL and letting the tool synthesise it beats hand-instantiating gates. Gate-level design is for understanding, not usually for shipping.

ProblemA 3-to-8 decoder drives eight chip selects from an address bus. A colleague reports that occasionally the wrong peripheral responds. The logic is provably correct. What is happening?

1. 1
   The decoder is combinational and correct in steady state: for any settled address, exactly one output asserts.
2. 2
   But the address bus bits do not change simultaneously. If the address goes from 011 to 100, all three bits change, and they arrive skewed by routing and driver differences.
3. 3
   During the transition the decoder may momentarily see 111, 001, 000 or other intermediate codes, and it will faithfully assert the corresponding chip select for a few nanoseconds each.
4. 4
   A chip select is an asynchronous, edge-sensitive control input on most peripherals. A 3 ns pulse can be enough to latch a write.
5. 5
   Quantify: if the bus skew is 2 ns and the decoder's propagation delay is 8 ns, the glitch window is roughly the skew, so glitches of up to about 2 ns can appear on the wrong outputs.
6. 6
   Fix 1 (the correct one): gate the decoder with a qualified strobe. Add an enable input to the decoder driven by a signal that only asserts after the address has settled. The 74HC138 has exactly this — three enable inputs — and this is why.
7. 7
   Fix 2 (synchronous): register the decoder outputs in flip-flops clocked after the address is stable. Glitches on a D input are harmless; only the value at the clock edge matters.
8. 8
   Fix 3 (wrong): adding an RC filter to the chip select. This slows the edge, causes a slow transition through the threshold region, and can make things worse by adding metastability risk.
9. 9
   General rule that falls out: never drive an asynchronous control input directly from unqualified combinational logic on a changing bus.

AnswerDecoding glitches during address transitions. Fix by gating the decoder with a settled strobe (the enable pins exist for this) or by registering the outputs. This is why address decoders in real designs always have an enable.

Tool: Digital (hneemann) with delay modelling, plus Logisim-evolution

• In Digital, build a 1-bit full adder from gates: Sum = A XOR B XOR Cin, Cout = A.B + Cin.(A XOR B).
• Wrap it as a reusable component: File > Save As inside your project folder, then place it as a sub-circuit four times to make a 4-bit ripple carry adder.
• Add a test case with vectors covering carry propagation, especially 1111 + 0001 which forces a carry through every stage.
• Enable gate delays: in Digital's circuit settings, gates have a configurable delay. Set a uniform delay and use the measurement graph (Analysis > Measurement Graph) to observe the output settling.
• Observe that the most significant sum bit settles later than the least significant. Count the gate levels along the carry chain and confirm the delay matches your count times the per-gate delay.
• Now build the glitch demo: a 3-to-8 decoder from gates, driven by three inputs. Add a small extra delay to one input (an even number of inverters in series works).
• Change the three inputs from 011 to 100 in a single simulation step and watch the outputs on the measurement graph. You should see a transient pulse on an output that should never have asserted.
• Add an enable input to the decoder and gate all outputs with it. Assert the enable only after the inputs settle. Confirm the glitch disappears.
• Repeat the adder in Logisim-evolution if you want a second tool's view; it also exports to VHDL/Verilog, which is a useful bridge if you continue into FPGA work.

• All About Circuits - Digital, combinational function blocksfreereading~150 minChapters on combinational logic functions, multiplexers, encoders and arithmetic circuits.
• nand2tetris Part I (project 1 and 2)freecourse~240 minFree course materials. Projects 1 and 2 have you build exactly these blocks (mux, demux, adder, ALU) with an automated test harness. Directly relevant and rigorously graded by the supplied tooling.
• Logisim-evolutionopen licencetoolGPL. A second open logic simulator with HDL export and FPGA download support. Useful if you plan to move to programmable logic later.
• 74HC138 and 74HC153 datasheetsfreedatasheet~30 minRead a real decoder and a real multiplexer datasheet. Note the enable inputs, the propagation delay table across supply voltage, and the output drive current.

Design, simulate and verify a 4-bit arithmetic and logic unit supporting at least four operations, with a full timing analysis and a demonstrated, then eliminated, glitch.

Deliverables

• A specification: the operations supported, the opcode encoding, the inputs and outputs including any flags (zero, carry, overflow, negative).
• A block diagram showing how the ALU decomposes into standard blocks (adder, mux, logic array), not a flat gate soup.
• A hierarchical implementation in Digital or Logisim-evolution using reusable sub-circuits, with the 1-bit slice built once and instantiated four times.
• An automated test-vector table covering: all four operations on representative operands, carry propagation through all four bits, two's complement overflow at the boundary, and the zero flag. Screenshot of the passing run.
• A critical-path analysis: identify the longest path through your design, count the gate levels, state the total delay under an assumed per-gate delay, and hence state the maximum clock frequency this ALU could support.
• A glitch demonstration: introduce skew on one input and capture a waveform showing a transient wrong value on an output that would be dangerous if it drove an asynchronous control input. Then show the fix (registered output or qualified enable) and capture the corrected waveform.
• A comparison: replace your ripple carry with a carry lookahead for the top two bits and report the change in gate count and in critical path length.

Acceptance criteria — how you know it is good enough

• The design is hierarchical: a 1-bit slice is built once and reused.
• Test vectors cover overflow and full carry propagation, not just typical cases.
• The critical path is identified specifically (naming the signal path), not merely estimated.
• A real glitch is captured on a waveform and then demonstrably eliminated.
• Flags are implemented correctly, including the distinction between carry and signed overflow.

If you want to push further

• Export the design to VHDL or Verilog from Logisim-evolution and read the generated code, comparing it to what you would have written by hand.
• Implement the same ALU as a lookup table in a ROM and compare size, delay and flexibility.

• I can identify whether a piece of logic is combinational or has accidentally become stateful.
• I design with standard blocks (mux, decoder, adder) rather than raw gates.
• I can find the critical path in a combinational block and convert it to a maximum frequency.
• I can explain, demonstrate and fix a decoding glitch.
• I know which destinations tolerate glitches and which do not.
• I verify combinational logic with exhaustive or boundary-focused test vectors.